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Part Number NPe405H Revision 1.01 - April 18, 2007
NPe405H
PowerNP NPe405H Embedded Processor
FEATURES
* PowerNPTM technology using an AMCC PowerPC(R) 405 32-bit RISC processor core operating up to 266 MHz PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications External bus for peripheral devices - Flash and ROM interface - Direct support for 8-, or 16-, or 32-bit SRAM and external peripherals - Up to 8 devices - External mastering supported DMA support for external peripherals, internal UARTs and memory - Scatter-gather chaining supported - Four channels PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Asynchronous PCI bus interface - Internal PCI bus arbiter which can be disabled for use with an external arbiter Four 10/100 Ethernet MACs supporting up to four external PHYs via MII, RMII, or SMII interfaces HDLC interface with 32 channels through two ports at up to 4.096 Mbps each or 8.192 Mbps for a single port HDLC interface with 8 channels through 8 ports at 2.048 Mbps maximum Programmable interrupt controller - Seven external and 49 internal - Edge triggered or level-sensitive - Positive or negative active - Non-critical or critical interrupt to processor core * * * * * * * *
Data Sheet
- Programmable critical interrupt priority ordering - Programmable critical interrupt vector Programmable timers Two serial ports (16550 compatible UART) One IIC interface General Purpose I/O (GPIO) available Supports JTAG for board level testing Internal processor local bus (PLB) runs at SDRAM interface frequency Supports PowerPC processor boot from PCI memory User accessible performance counters
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DESCRIPTION
Designed specifically to address embedded applications, the NPe405H provides a high-performance, lowpower solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus bridge, Ethernet EMACs, HDLC controllers, external bus controller for ROM, Flash, and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: CMOS SA-12E 0.25 m (0.18 m Leff) Package: 35mm, 580-ball enhanced plastic ball grid array (E-PBGA) Power (typical): 2.3 W at 133 MHz, 2.9W at 200MHz, 3.4W at 266MHz
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TABLE OF CONTENTS
FEATURES .............................................................................................................................................................. 1 DESCRIPTION ........................................................................................................................................................ 1 ORDERING, PVR, AND JTAG INFORMATION ...................................................................................................... 5 AMCC Part Number Key ................................................................................................................................... 5 NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM ......................................................... 6 ADDRESS MAP SUPPORT .................................................................................................................................... 7 SYSTEM ADDRESS MAP ....................................................................................................................................... 7 DCR ADDRESS MAP .............................................................................................................................................. 8 PLB TO PCI BRIDGE .............................................................................................................................................. 9 SDRAM MEMORY CONTROLLER ....................................................................................................................... 10 EXTERNAL BUS CONTROLLER (EBC) .............................................................................................................. 10 DMA CONTROLLER ............................................................................................................................................. 11 SERIAL INTERFACE ............................................................................................................................................ 11 IIC BUS INTERFACE ............................................................................................................................................ 11 IIC EEPROM CONTROLLER ................................................................................................................................ 11 HDLCEX INTERFACE ........................................................................................................................................... 12 HDLCMP INTERFACE .......................................................................................................................................... 12 GENERAL PURPOSE IO (GPIO) CONTROLLER ................................................................................................ 12 UNIVERSAL INTERRUPT CONTROLLER (UIC) ................................................................................................. 12 10/100 MBPS ETHERNET MAC ........................................................................................................................... 13 JTAG ..................................................................................................................................................................... 13 PERFORMANCE COUNTERS .............................................................................................................................. 13 35 MM, 580-BALL E-PBGA PACKAGE ............................................................................................................... 14 SIGNAL LISTS ...................................................................................................................................................... 15 SIGNALS LISTED ALPHABETICALLY ................................................................................................................ 15 SIGNALS LISTED BY BALL ASSIGNMENT ........................................................................................................ 32 SIGNAL DESCRIPTION ........................................................................................................................................ 41 PIN SUMMARY ..................................................................................................................................................... 41 Multiplexed Pins .............................................................................................................................................. 41 Multipurpose Pins ............................................................................................................................................ 41 Initialization Strapping ...................................................................................................................................... 41 Pull-up and Pull-down Resistors ...................................................................................................................... 42 Unused I/Os ..................................................................................................................................................... 42 External Peripheral Bus Control Signals ......................................................................................................... 42 SIGNAL FUNCTIONAL DESCRIPTION ................................................................................................................ 43 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 52 PACKAGE THERMAL SPECIFICATIONS ........................................................................................................... 52 RECOMMENDED DC OPERATING CONDITIONS .............................................................................................. 53 5 V-TOLERANT I/O INPUT CURRENT ................................................................................................................. 54 INPUT CAPACITANCE ......................................................................................................................................... 54 DC ELECTRICAL CHARACTERISTICS ............................................................................................................... 55
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TEST CONDITIONS .............................................................................................................................................. 55 CLOCKING SPECIFICATIONS ............................................................................................................................. 56 CLOCKING WAVEFORM ...................................................................................................................................... 56 SPREAD SPECTRUM CLOCKING ....................................................................................................................... 57 PERIPHERAL INTERFACE CLOCK TIMINGS ..................................................................................................... 58 INPUT SETUP AND HOLD WAVEFORM ............................................................................................................. 59 OUTPUT DELAY AND FLOAT TIMING WAVEFORM ......................................................................................... 59 I/O SPECIFICATIONS--ALL ................................................................................................................................ 60 I/O SPECIFICATIONS(A)--133 AND 200 MHZ .................................................................................................... 62 I/O SPECIFICATIONS(A)--266 MHZ .................................................................................................................... 65 INITIALIZATION .................................................................................................................................................... 68 Strapping ......................................................................................................................................................... 68 STRAPPING PIN ASSIGNMENTS ........................................................................................................................ 68 EEPROM ......................................................................................................................................................... 68 DOCUMENT REVISION HISTORY ....................................................................................................................... 69
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LIST OF FIGURES
Figure 1. NPe405H Embedded Controller Functional Block Diagram ..................................................................... 6 Figure 2. 35mm, 580-Ball E-PBGA Package ......................................................................................................... 14 Figure 3. 5V-Tolerant I/O Input Current ................................................................................................................. 54 Figure 4. Clocking Waveform ................................................................................................................................. 56 Figure 5. Input Setup and Hold Waveform ............................................................................................................. 59 Figure 6. Output Delay and Float Timing Waveform .............................................................................................. 59
LIST OF TABLES
Table 1. System Address Map 4GB Total System Memory ..................................................................................... 7 Table 2. DCR Address Map 4KB Device Configuration Register ............................................................................. 8 Table 3. Signals Listed Alphabetically ................................................................................................................... 15 Table 4. Signals Listed by Ball Assignment ........................................................................................................... 32 Table 5. Pin Summary ........................................................................................................................................... 41 Table 6. Signal Functional Description .................................................................................................................. 43 Table 7. Absolute Maximum Ratings ..................................................................................................................... 52 Table 8. Package Thermal Specifications .............................................................................................................. 52 Table 9. Recommended DC Operating Conditions ................................................................................................ 53 Table 10. Input Capacitance .................................................................................................................................. 54 Table 11. DC Electrical Characteristics .................................................................................................................. 55 Table 12. Clocking Specifications .......................................................................................................................... 56 Table 13. Peripheral Interface Clock Timings ........................................................................................................ 58 Table 14. I/O Specifications--All ........................................................................................................................... 60 Table 15. I/O Specifications--133 and 200MHz .................................................................................................... 62 Table 16. I/O Specifications--266MHz .................................................................................................................. 65 Table 17. Strapping Pin Assignments .................................................................................................................... 68
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ORDERING, PVR, AND JTAG INFORMATION
Product Name NPe405H NPe405H NPe405H NPe405H NPe405H NPe405H 1 Order Part Number NPE405H-3BA133C NPE405H-3BA133CZ NPe405H-3BA200C NPe405H-3BA200CZ NPe405H-3BA266C NPe405H-3BA266CZ Processor Frequency 133MHz 133MHz 200MHz 200MHz 266MHz 266MHz Package 35mm, 580 E-PBGA 35mm, 580 E-PBGA 35mm, 580 E-PBGA 35mm, 580 E-PBGA 35mm, 580 E-PBGA 35mm, 580 E-PBGA Rev Level A A A A A A PVR Value 0x41410140 0x41410140 0x41410140 0x41410140 0x41410140 0x41410140 JTAG ID 0x04267049 0x04267049 0x04267049 0x04267049 0x04267049 0x04267049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
This section provides the part numbering nomenclature for the NPe405H. For availability, contact your local AMCC sales office. The part number contains a part modifier. This modifier provides for identification of future enhancements (for example, higher performance). Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the NPe405H User's Manual for details on the register content. AMCC Part Number Key
NPe405H-3BA200Cx
Shipping Package Blank = Tray Z = Tape and reel AMCC Part Number Grade 3 Reliability Operational Case Temperature Range (-40C to +85C) Processor Speed 133MHz 200MHz 266MHz Revision Level
Package (E-PBGA)
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NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM
Figure 1. NPe405H Embedded Controller Functional Block Diagram
Universal Interrupt Controller x2
Clock Control Reset Timers MMU
Power Mgmt DCRs
See Peripheral Interface
PPC405 Processor Core JTAG 8KB D-Cache DCU Trace ICU
DCR Bus
GPIO x2
IIC IEC
UART x2
16KB I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA Controller (4-Channel)
OPB Bridge
Processor Local Bus (PLB) Ethernet x4
MAL0 MAL1 SDRAM Controller 13-bit addr 32-bit data External Bus Controller External Bus Master Controller PCI Bridge
HDLCEX
MAL2
HDLCMP
ZMII
32-bit addr 32-bit data
66 MHz max (async) Two 32-channel ports 8 MII, RMII, single-channel ports SMII
The NPe405H is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way to generate complex ASICs using IBM CoreConnectTM Bus Architecture.
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ADDRESS MAP SUPPORT
The NPe405H incorporates two separate address maps. The first is a fixed processor address map that serves the PowerPC family of processors. This address map defines the possible contents of various address regions which the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the NPe405H processor through the use of mtdcr and mfdcr commands.
SYSTEM ADDRESS MAP
Table 1. System Address Map 4GB Total System Memory
Function Subfunction SDRAM, External peripherals, and PCI memory Note: Any of the address ranges listed at right may be use for any of the above functions. 1 Start Address 0x00000000 0xE8010000 0xEC000000 0xEEE00000 0xEF500000 0xEF900000 Boot-up External peripheral bus boot PCI boot PCI I/O PCI I/O PCI Configuration registers Interrupt Acknowledge and special cycle Local configuration registers UART0 UART1 IIC0 OPB arbiter GPIO0 controller registers GPIO1 controller registers Internal peripherals Ethernet MAC 0 registers Ethernet MAC 1 registers Ethernet MAC 2 registers Ethernet MAC 3 registers ZMII control registers HDLCEX HDLCMP 2 0xFFE00000 0xFFFE0000 0xE8000000 0xE8800000 0xEEC00000 0xEED00000 0xEF400000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 0xEF600780 0xEF600800 0xEF600900 0xEF600A00 0xEF600B00 0xEF600C10 0xEF610000 0xEF620000 End Address 0xE7FFFFFF 0xE87FFFFF 0xEEBFFFFF 0xEF3FFFFF 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xE800FFFF 0xEBFFFFFF 0xEEC00007 0xEED00003 0xEF40003F 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F 0xEF6007FF 0xEF6008FF 0xEF6009FF 0xEF600AFF 0xEF600BFF 0xEF600C1F 0xEF61FFFF 0xEF62FFFF Size 3712MB 8MB 44MB 6MB 1MB 263MB 2MB 128KB 64KB 56MB 8B 4B 64B 8B 8B 32B 64B 128B 128B 256B 256B 256B 256B 16B 64KB 64KB
General use
Notes: 1. When external peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above. 3. After the boot process, software may reassign the boot memory regions for other uses. 4. All address ranges not listed above are reserved.
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DCR ADDRESS MAP
Table 2. DCR Address Map 4KB Device Configuration Register
Function DCR address space1 Reserved Memory controller registers External bus controller registers Reserved PLB registers Performance counters Reserved OPB bridge-out registers Reserved Clock, control and reset Power management Interrupt controller 0 Interrupt controller 1 Reserved Miscellaneous DMA controller registers Reserved MAL0 registers (Ethernet) MAL1 registers (HDLCEX) MAL2 registers (HDLCMP) Reserved Start 0x000 End 0x3FF Size 1KW (4KB)1 16W 2W 2W 108W 16W 2W 14W 8W 8W 8W 8W 16W 16W 16W 16W 64W 64W 128W 128W 128W 256W
0x000 0x010 0x012 0x014 0x080 0x090 0x092 0x0A0 0x0A8 0x0B0 0x0B8 0x0C0 0x0D0 0x0E0 0x0F0 0x100 0x140 0x180 0x200 0x280 0x300
0x00F 0x011 0x013 0x07F 0x08F 0x091 0x09F 0x0A7 0x0AF 0x0B7 0x0BF 0x0CF 0x0DF 0x0EF 0x0FF 0x13F 0x17F 0x1FF 0x27F 0x2FF 0x3FF
Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB).
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PLB TO PCI BRIDGE
The PLB to PCI bridge provides a mechanism for connecting PCI devices to the processor, peripherals, and memory. This interface is PCI Specification rev 2.2 compliant. Features include: * * * * * Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is optional and can be disabled for systems which employ an external arbiter. PCI bus frequency up to 66MHz - Asynchronous operation from 1/8 PLB frequency to 66MHz maximum 32-bit PCI Address/Data Bus Power Management: - PCI Bus Power Management v1.1 compliant Buffering between PLB and PCI: - PCI Target 64-byte write post buffer - PCI Target 96-byte read prefetch buffer - PLB Slave 32-byte write post buffer - PLB Slave 64-byte read prefetch buffer Error tracking/status Supports PCI Target side configuration Supports processor access to all PCI address spaces: - Single-byte PCI I/O reads and writes - PCI memory single-beat and prefetch-burst reads and single-beat writes - Single-byte PCI configuration reads and writes (type 0 and type 1) - PCI interrupt acknowledge - PCI special cycle Supports PCI target access to all PLB address spaces Supports PowerPC processor boot from PCI memory
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SDRAM MEMORY CONTROLLER
The NPe405H Memory Controller provides a low latency access path to SDRAM memory. The memory controller supports four logical banks. Up to 256MB per bank are supported, for a maximum of 1GB total. Memory access and refresh timing, address and bank sizes, and memory addressing modes are programmable. Features include: * * * * * * * * * * * * * 11x8 to 13x11 row-column address modes (2- and 4-bank devices supported) Memory bus operates at same frequency as PLB 32-bit memory interface support Programmable address range for each bank of memory - 4GB address space Industry standard 168-pin DIMMS are supported (some configurations) 200 MHz NPe405H supports up to 100 MHz memory with PC100 support 266 MHz NPe405H supports up to 133 MHz memory with PC133 support 4MB to 256MB per bank Programmable timing Auto refresh Page Mode Accesses with up to 4 open pages Power Management (self-refresh) Error Checking and Correction (ECC) support - Standard single error correct, double error detect coverage - Aligned nibble error detect - Address error logging
EXTERNAL BUS CONTROLLER (EBC)
* * * * * * * Supports eight ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported Up to 66.66MHz operation Burst and non-burst devices 8-, 16-, 32-bit byte-addressable data bus width support Latch data on Ready, Synchronous or Asynchronous Programmable 2K clock-cycle time-out counter with disable for Ready Programmable access timing per device - 0-255 wait states for non-bursting devices - 0 -31 Burst Wait States for first access and up to 7 Wait States for subsequent accesses - Programmable chip select assertion/negation relative to driving address bus - Programmable output and write-enable assertion/negation relative to assertion of chip select Programmable address mapping Peripheral device wait via "Ready" External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control
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DMA CONTROLLER
* Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers Four channels Scatter/Gather capability for programming multiple DMA operations 8-, 16-, 32-bit peripheral support (OPB and external bus attached) 32-bit addressing Address increment or decrement Internal 32-byte data buffering capability Supports internal and external peripherals Support for memory mapped peripherals Support for peripherals running on slower frequency buses
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SERIAL INTERFACE
* * * * * * * Two 8-pin UART interfaces provided Selectable internal or external serial clock to allow wide range of baud rates Register compatibility with NS16550 register set Complete status reporting capability Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode Fully programmable serial-interface characteristics Supports DMA using internal DMA engine
IIC BUS INTERFACE
* * * * * * * * * * * * Compliant with Phillips(R) Semiconductors I2C Specification, dated 1995 Operation at 100kHz or 400kHz 8-bit data 10- or 7-bit address Slave transmitter and receiver Master transmitter and receiver Multiple bus masters Supports fixed VDD IIC interface Two independent 4 x 1 byte data buffers One programmable interrupt request signal Provides full management of all IIC bus protocol Programmable error recovery
IIC EEPROM CONTROLLER
Supports setting of processor configuration from serial EEPROM during system reset.
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HDLCEX INTERFACE
* * * * * 32-channel HDLC controller Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 4.096 Mbps per port or 8.192 Mbps when using a single port Supports HDLC protocol as well as a Transparent mode For a single channel per port, autonomous management of I-Frames and S-Frames of the Normal Response mode (NRM) protocol on one channel per port. U-frames are handled by software. Supports software emulation of NRM on all channels
HDLCMP INTERFACE
* * * * HDLC controller provides eight full-duplex serial ports Up to 2.048Mbps data rate Supports HDLC protocol as well as a Transparent mode Software emulation of NRM
GENERAL PURPOSE IO (GPIO) CONTROLLER
* Two GPIO controllers - 32-signal system GPIO (GPIO0) - 32-signal communications GPIO (GPIO1) Most GPIOs are pin-shared with other functions. Configuration registers are provided to determine whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. Both GPIO functions have 32 I/Os. Each GPIO output is separately programmable to emulate an open-drain driver (drives to zero, three-stated if output bit is 1)
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UNIVERSAL INTERRUPT CONTROLLER (UIC)
Two cascaded Universal Interrupt Controllers (UICs) provide the control, status, and communications necessary for the interrupt sources and the PowerPC processor. Features include: * * * * * * Seven external and 49 internal interrupts Edge triggered or level-sensitive Positive or negative active Selectable non-critical or critical interrupt requests to the PPC405 processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector generation for reduced latency interrupt handling
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10/100 MBPS ETHERNET MAC
* * Four units capable of full- and half-duplex, 10 Mbps or 100 Mbps operation Integrated ZMII Bridge supports use of MII, SMII or RMII connections to external PHYs (PHYs not included on chip) - Reduced Media Independent Interface (RMII) or Serial Media Independent Interface (SMII) for one to four PHY applications - Media Independent Interface (MII) for single or dual PHY applications Dedicated media access layer (MAL) provides DMA support
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JTAG
* * * IEEE 1149.1 Test Access Port Debugger support JTAG boundary scan support (BSDL file available)
PERFORMANCE COUNTERS
A series of software accessible PLB transaction event counters that can be used to analyze PLB performance.
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35 MM, 580-BALL E-PBGA PACKAGE
Figure 2. 35mm, 580-Ball E-PBGA Package
Top View
Gold gate release corresponds to A01 ball location Note: All dimensions are in mm.
Bottom View
AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AP
35.0 1.0
0.60 nom 0.30 nom
1.0
35.0
01 03 05 07 09 11 13 15 17 19 21 23 25 27 29 31 33 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34
0.60 Solder Ball
2.65 max
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SIGNAL LISTS
The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal or signals in brackets. Multiplexed signals appear alphabetically multiple times in the list--once for each signal name on the ball. The page number listed gives the page in "Signal Functional Description" on page 43 where the signals in the indicated interface group begin.
SIGNALS LISTED ALPHABETICALLY
Table 3. Signals Listed Alphabetically (Sheet 1 of 17)
Signal Name AVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 [BE0]PCIC0 [BE1]PCIC1 [BE2]PCIC2 [BE3]PCIC3 BusReq CAS ClkEn0 ClkEn1 [DMAAck0]GPIO0_13 [DMAAck1]GPIO0_14 [DMAAck2]GPIO0_15 [DMAAck3]GPIO0_16[PerCS5] [DMAReq0]GPIO0_09 [DMAReq1]GPIO0_10 [DMAReq2]GPIO0_11 [DMAReq3]GPIO0_12[PerCS4] DQM0 DQM1 DQM2 DQM3 DQMCB ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMC0MDClk Ball P31 AN31 AM31 AL21 AP23 AM22 AN23 D01 B06 B10 C15 H03 AN22 AP21 AN21 AB34 AB33 AA31 AC34 AA34 W32 AA33 AA32 AN20 AN15 AP12 AN09 AM20 AP24 AN24 AM24 AN25 AP26 AM25 AN26 AL25 C21 Ethernet 44 SDRAM 46 SDRAM 46 SDRAM 46 External Slave Peripheral Bus 47 External Slave Peripheral Bus 47 External Master Peripheral Bus SDRAM SDRAM 49 46 46 PCI 43 SDRAM 46 Power SDRAM Interface Group Page 51 46
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Table 3. Signals Listed Alphabetically (Sheet 2 of 17)
Signal Name EMC0MDIO [EMC0Sync]EMC0TxEn[EMC0Tx0En] EMC0TxD0[EMC0Tx0D0][EMC0Tx0D] EMC0TxD1[EMC0Tx0D1][EMC0Tx1D] EMC0TxD2[EMC0Tx1D0][EMC0Tx2D] EMC0TxD3[EMC0Tx1D1][EMC0Tx3D] EMC0TxEn[EMC0Tx0En][EMC0Sync] EMC0TxErr[EMC0Tx1En] [EMC0Tx0En]EMC0TxEn[EMC0Sync] [EMC0Tx1En]EMC0TxErr [EMC1TxEn][EMC1Tx2En]GPIO1_12[HDLCMPTxEn6] [EMC1TxErr][EMC1Tx3En]GPIO1_11[HDLCMPTxData6] [EMC1Tx2En][EMC1TxEn]GPIO1_12[HDLCMPTxEn6] [EMC1Tx3En][EMC1TxErr]GPIO1_11[HDLCMPTxData6] [EMC1TxD0][EMC1Tx2D0]GPIO1_04[HDLCMPRxData4] [EMC1TxD1][EMC1Tx2D1]GPIO1_05[HDLCMPTxClk5] [EMC1TxD2][EMC1Tx3D0]GPIO1_06[HDLCMPTxData5] [EMC1TxD3][EMC1Tx3D1]GPIO1_07[HDLCMPTxEn5] [EOT0/TC0]GPIO0_24 [EOT1/TC1]GPIO0_25 [EOT2/TC2]GPIO0_26 [EOT3/TC3]GPIO0_27[PerCS7] ExtAck ExtReq ExtReset Ball B21 D21 A24 B23 C22 A23 D21 A22 D21 A22 B30 C29 B30 C29 A28 C27 B28 D27 AF34 AE32 AF33 AE31 H02 J03 K03 External Master Peripheral Bus External Master Peripheral Bus External Master Peripheral Bus 49 49 49 External Slave Peripheral Bus 47 Ethernet 44 Ethernet 44 Ethernet Ethernet Ethernet 44 44 44 Ethernet 44 Ethernet Ethernet Interface Group Page 44 44
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Table 3. Signals Listed Alphabetically (Sheet 3 of 17)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball A01 A02 A06 A10 A15 A20 A25 A29 A33 A34 B01 B02 B33 B34 C03 C32 D04 D12 D17 D18 D23 D31 F01 F34 K01 K34 M04 M31 N13-N22 P13-P22 R01 R13-R22 R34 T13-T22 U04 U13-U22 U31 Power Note: Balls N13-N22, P13-P22, R13-R22, T13T22, U13-U22, V13-V22, W13-W22, Y13Y22, AA13-AA22, and AB13-AB22 are also thermal balls. 51 Interface Group Page
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Table 3. Signals Listed Alphabetically (Sheet 4 of 17)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND [Gnt]PCIReq0 Ball V04 V13-V22 V31 W13-W22 Y13-Y22 Y01 Y34 AA13-AA22 AB13-AB22 AC04 AC31 AE01 AE34 AJ01 AJ34 AL04 AL12 AL17 AL18 AL23 AL31 AM03 AM17 AM32 AN01 AN02 AN33 AN34 AP01 AP02 AP06 AP10 AP15 AP20 AP25 AP29 AP33 AP34 A19 PCI 43 Power Note: Balls N13-N22, P13-P22, R13-R22, T13T22, U13-U22, V13-V22, W13-W22, Y13-Y22, AA13-AA22, and AB13-AB22 are also thermal balls. Interface Group Page
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 5 of 17)
Signal Name GPIO0_00 GPIO0_01[TS1E] GPIO0_02[TS2E] GPIO0_03[TS1O] GPIO0_04[TS2O] GPIO0_05[TS3] GPIO0_06[TS4] GPIO0_07[TS5] GPIO0_08[TS6] GPIO0_09[DMAReq0] GPIO0_10[DMAReq1] GPIO0_11[DMAReq2] GPIO0_12[DMAReq3][PerCS4] GPIO0_13[DMAAck0] GPIO0_14[DMAAck1] GPIO0_15[DMAAck2] GPIO0_16[DMAAck3][PerCS5] GPIO0_17[IRQ0] GPIO0_18[IRQ1] GPIO0_19[IRQ2] GPIO0_20[IRQ3] GPIO0_21[IRQ4] GPIO0_22[IRQ5] GPIO0_23[IRQ6][PerCS6] GPIO0_24[EOT0/TC0] GPIO0_25[EOT1/TC1] GPIO0_26[EOT2/TC2] GPIO0_27[EOT3/TC3][PerCS7] GPIO0_28[PerCS1] GPIO0_29[PerCS2] GPIO0_30[PerCS3] GPIO0_31[TrcClk] Ball U34 U33 V33 V34 W34 W33 V32 Y33 Y32 AA34 W32 AA33 AA32 AB34 AB33 AA31 AC34 AB32 AC33 AD34 AC32 AD33 AD32 AE33 AF34 AE32 AF33 AE31 AG34 AF32 AG33 AH34 System 51 Interface Group Page
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Revision 1.01 - April 18, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 6 of 17)
Signal Name GPIO1_00[HDLCMPTxClk4][PHY1RxD0][PHY1Rx2D0] GPIO1_01[HDLCMPTxData4][PHY1RxD1][PHY1Rx2D1] GPIO1_02[HDLCMPTxEn4][PHY1RxD2][PHY1Rx3D0] GPIO1_03[HDLCMPRxClk4][PHY1RxD3][PHY1Rx3D1] GPIO1_04[HDLCMPRxData4][EMC1TxD0][EMC1Tx2D0] GPIO1_05[HDLCMPTxClk5][EMC1TxD1][EMC1Tx2D1] GPIO1_06[HDLCMPTxData5][EMC1TxD2][EMC1Tx3D0] GPIO1_07[HDLCMPTxEn5][EMC1TxD3][EMC1Tx3D1] GPIO1_08[HDLCMPRxClk5][PHY1RxErr][PHY1Rx2Er] GPIO1_09[HDLCMPRxData5][PHY1RxDV][PHY1CrS3DV] GPIO1_10[HDLCMPTxClk6][PHY1CrS][PHY1CrS2DV] GPIO1_11[HDLCMPTxData6][EMC1TxErr][EMC1Tx3En] GPIO1_12[HDLCMPTxEn6][EMC1TxEn][EMC1Tx2En] GPIO1_13[HDLCMPRxClk6][PHY1RxClk] GPIO1_14[HDLCMPRxData6][PHY1Col][PHY1Rx3Er] GPIO1_15[HDLCMPTxClk7] GPIO1_16[HDLCMPTxData7] GPIO1_17[HDLCMPTxEn7][PHY1TxClk] GPIO1_18[HDLCMPRxClk7] GPIO1_19[HDLCMPRxData7] GPIO1_20[HDLCMPTxEn0][UART1_CTS] GPIO1_21[HDLCMPTxEn1][UART1_DSR] GPIO1_22[HDLCMPTxEn2][UART1_DCD] GPIO1_23[HDLCMPTxEn3][UART1_RI] GPIO1_24[HDLCEXTxEnA][UART1_RTS] GPIO1_25[HDLCEXTxEnB][UART1_DTR] GPIO1_26[UART0_CTS] GPIO1_27[UART0_DSR] GPIO1_28[UART0_DCD] GPIO1_29[UART0_RI]x GPIO1_30[UART0_RTS] GPIO1_31[UART0_DTR] Halt HDLCEXRxClk HDLCEXRxDataA HDLCEXRxDataB HDLCEXRxFS HDLCEXTxClk HDLCEXTxDataA HDLCEXTxDataB [HDLCEXTxEnA]GPIO1_24[UART1_RTS] [HDLCEXTxEnB]GPIO1_25[UART1_DTR] HDLCEXTxFS Ball D25 A27 C26 B27 A28 C27 B28 D27 C28 B29 A30 C29 B30 A31 B32 D29 C30 A32 B31 C31 D33 C34 E32 F31 C33 D34 E33 F32 E34 F33 G32 H31 N33 AJ31 AK33 AL34 AM33 AL32 AK32 AM34 C33 D34 AL33 System HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel 51 44 44 44 44 44 44 44 System 51 Interface Group Page
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 7 of 17)
Signal Name HDLCMPRxClk0 HDLCMPRxClk1 HDLCMPRxClk2 HDLCMPRxClk3 [HDLCMPRxClk4]GPIO1_03[PHY1RxD3][PHY1Rx3D1] [HDLCMPRxClk5]GPIO1_08[PHY1RxErr][PHY1Rx2Er] [HDLCMPRxClk6]GPIO1_13[PHY1RxClk] [HDLCMPRxClk7]GPIO1_18] HDLCMPRxData0 HDLCMPRxData1 HDLCMPRxData2 HDLCMPRxData3 [HDLCMPRxData4]GPIO1_04[EMC1TxD0][EMC1Tx2D0] [HDLCMPRxData5]GPIO1_09[PHY1RxDV][PHY1CrS3DV] [HDLCMPRxData6]GPIO1_14[PHY1Col][PHY1Rx3Er] [HDLCMPRxData7]GPIO1_19 HDLCMPTxClk0 HDLCMPTxClk1 HDLCMPTxClk2 HDLCMPTxClk3 [HDLCMPTxClk4]GPIO1_00[PHY1RxD0][PHY1Rx2D0] [HDLCMPTxClk5]GPIO1_05[EMC1TxD1][EMC1Tx2D1] [HDLCMPTxClk6]GPIO1_10[PHY1CrS][PHY1CrS2DV] [HDLCMPTxClk7]GPIO1_15 HDLCMPTxData0 HDLCMPTxData1 HDLCMPTxData2 HDLCMPTxData3 [HDLCMPTxData4]GPIO1_01[PHY1RxD1][PHY1Rx2D1] [HDLCMPTxData5]GPIO1_06[EMC1TxD2][EMC1Tx3D0] [HDLCMPTxData6]GPIO1_11[EMC1TxErr][EMC1Tx3En] [HDLCMPTxData7]GPIO1_16 [HDLCMPTxEn0]GPIO1_20[UART1_CTS] [HDLCMPTxEn1[GPIO1_21[UART1_DSR] [HDLCMPTxEn2]GPIO1_22[UART1_DCD] [HDLCMPTxEn3]GPIO1_23[UART1_RI] [HDLCMPTxEn4]GPIO1_02[PHYRx3D0] [HDLCMPTxEn5]GPIO1_07[EMC0Tx3D1] [HDLCMPTxEn6]GPIO1_12[EMC0Tx2En] [HDLCMPTxEn7]GPIO1_17[PHY1TxClk] HoldAck HoldPri HoldReq IICSCL[IECSCL] IICSDA[IECSDA] Ball G33 H33 H34 N34 B27 C28 A31 B31 G34 J32 K31 P32 A28 B29 B32 C31 P33 P34 R33 T33 D25 C27 A30 D29 T32 R32 U32 T34 A27 B28 C29 C30 D33 C34 E32 F31 C26 D27 B30 A32 H01 K04 J02 AK34 AJ32 Internal Peripheral Bus 49 External Master Peripheral Bus 49 HDLC 8-Port 44 HDLC 8-Port 44 HDLC 8-Port 44 HDLC 8-Port 44 HDLC 8-Port 44 HDLC 8-Port 44 HDLC 8-Port 44 HDLC 8-Port 44 HDLC 8-Port 44 Interface Group Page
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 8 of 17)
Signal Name [IRQ0]GPIO0_17 [IRQ1]GPIO0_18 [IRQ2]GPIO0_19 [IRQ3]GPIO0_20 [IRQ4]GPIO0_21 [IRQ5]GPIO0_22 [IRQ6]GPIO0_23[PerCS6] MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 Ball AB32 AC33 AD34 AC32 AD33 AD32 AE33 AP27 AM26 AN27 AN28 AM28 AN29 AP30 AM29 AN30 AP31 AL29 AM30 AP32 AM27 AP28 SDRAM 46 SDRAM Note: During a CAS cycle MemAddr00 is the least significant bit (lsb) on this bus. 46 Interrupts 50 Interface Group Page
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 9 of 17)
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AM18 AN19 AP19 AP18 AN18 AN17 AP16 AN16 AM15 AP14 AM16 AN14 AM14 AP13 AN13 AL14 AM13 AN12 AP11 AM12 AN11 AN10 AP09 AM10 AL10 AP08 AM09 AN08 AP07 AM08 AN07 AL08 SDRAM Notes: 1. MemData00 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb) Interface Group Page 46
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 10 of 17)
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball A11 B05 B22 C08 C16 D05 D07 D09 D11 D24 D26 D28 D30 E03 E04 E31 F03 Power G04 G31 J04 J31 L04 L31 L32 M32 M34 AD04 AD31 AF04 AF31 AH04 AH31 AK04 AK31 51 Interface Group Page
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 11 of 17)
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball AL05 AL07 AL09 AL11 AL24 AL26 AL27 AL28 AL30 AM06 AM11 AM19 AM23 AN32 AP17 Power 51 Interface Group Page
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 12 of 17)
Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0[BE0] PCIC1[BE1] PCIC2[BE2] PCIC3[BE3] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel Ball H04 G01 G02 G03 F02 F04 E01 D03 C01 C02 B03 A03 C04 A04 A05 C06 C11 C12 B12 A12 A13 B13 C14 B14 B15 B16 A16 C17 B17 C18 B18 A18 D01 B06 B10 C15 B11 A08 C10 B19 A17 D06 D10 C13 D14 A14 PCI 43 PCI 43 PCI PCI PCI 43 43 43 PCI 43 PCI Note: PCIAD31 is the most significant bit (msb) on this bus. 43 Interface Group Page
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 13 of 17)
Signal Name PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 Ball C05 B09 B07 A07 A19 D02 E02 B04 C07 A09 B20 D08 B08 C09 AD02 AC03 AD01 AC02 AB03 AC01 AA04 AB02 AB01 AA03 AA02 W03 AA01 Y03 Y02 V03 W02 W01 V01 V02 U02 U01 T01 T02 U03 R02 R03 P01 T03 P02 P03 N01 External Slave Peripheral 47 PCI PCI PCI PCI 43 43 43 43 PCI 43 PCI PCI PCI PCI Interface Group Page 43 43 43 43
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 14 of 17)
Signal Name PerBLast PerClk PerCS0 [PerCS1]GPIO0_28 [PerCS2]GPIO0_29 [PerCS3]GPIO0_30 [PerCS4]GPIO0_12[DMAReq3] [PerCS5]GPIO0_16[DMAAck3] [PerCS6]GPIO0_23[IRQ6] [PerCS7]GPIO0_27[EOT3/TC3] PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE Ball L03 K02 M02 AG34 AF32 AG33 AA32 AC34 AE33 AE31 AM07 AN06 AP05 AN05 AP04 AN03 AL06 AM05 AN04 AM04 AL03 AL02 AM01 AK03 AJ04 AM02 AK02 AJ03 AK01 AJ02 AH03 AG04 AH02 AG03 AG02 AF03 AG01 AE04 AF02 AE03 AF01 AE02 J01 L01 External Slave Peripheral Bus External Slave Peripheral Bus 49 47 External Slave Peripheral Bus Note: PerData00 is the most significant bit (msb) on this bus. 47 External Slave Peripheral Bus 47 Interface Group External Slave Peripheral Bus External Slave Peripheral Bus Page 47 47
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 15 of 17)
Signal Name PerPar0 PerPar1 PerPar2 PerPar3 PerR/W PerReady PerWBE0 PerWBE1 PerWBE2 PerWBE3 [PerWE]PCIINT PHY0Col[PHY0Rx1Er] PHY0CrS[PHY0CrS0DV] [PHY0CrS0DV]PHY0CrS [PHY0CrS1DV]PHY0RxDV [PHY0RefClk]PHY0TxClk PHY0RxClk PHY0RxD0[PHY0Rx0D0][PHY0Rx0D] PHY0RxD1[PHY0Rx0D1][PHY0Rx1D] PHY0RxD2[PHY0Rx1D0][PHY0Rx2D] PHY0RxD3[PHY0Rx1D1][PHY0Rx3D] PHY0RxDV[PHY0CrS1DV] PHY0RxErr[PHY0Rx0Er] [PHY0Rx0Er]PHY0RxErr [PHY0Rx1Er]PHY0Col PHY0TxClk[PHY0RefClk] [PHY1Col][PHY1Rx3Er]GPIO1_14[HDLCMPRxData6] [PHY1CrS][PHY1CrS2DV]GPIO1_10[HDLCMPTxClk6] [PHY1CrS2DV][PHY1CrS]GPIO1_10[HDLCMPTxClk6] [PHY1CrS3DV][PHY1RxDV]GPIO1_09[HDLCMPRxData5] [PHY1RxClk]GPIO1_13[HDLCMPRxClk6] [PHY1RxDV][PHY1CrS3DV]GPIO1_09[HDLCMPRxData5] [PHY1RxD0][PHY1Rx2D0]GPIO1_00[HDLCMPTxClk4] [PHY1RxD1][PHY1Rx2D1]GPIO1_01[HDLCMPTxData4] [PHY1RxD2][PHY1Rx3D0]GPIO1_02[HDLCMPTxEn4] [PHY1RxD3][PHY1Rx3D1]GPIO1_03[HDLCMPRxClk4] [PHY1RxErr][PHY1Rx2Er]GPIO1_08[HDLCMPRxClk5] [PHY1Rx2Er][PHY1RxErr]GPIO1_08[HDLCMPRxClk5] [PHY1Rx3Er][PHY1Col]GPIO1_14[HDLCMPRxData6] [PHY1TxClk]GPIO1_17[HDLCMPTxEn7] RAS [Req]PCIGnt0 Reserved SysClk SysErr SysReset L33 K32 J33 Ball AP03 AL01 AH01 AD03 M03 L02 N02 P04 M01 N03 C05 C20 A21 A21 C23 C19 B24 B26 C25 A26 B25 C23 C24 C24 C20 C19 B32 A30 A30 B29 A31 B29 D25 A27 C26 B27 C28 C28 B32 A32 AP22 B19 Ethernet Ethernet Ethernet SDRAM PCI Other System System System 44 44 44 46 43 51 51 51 51 Ethernet 44 Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet 44 44 44 44 44 44 44 44 44 44 Ethernet 44 External Slave Peripheral Bus Ethernet Ethernet Ethernet Ethernet Ethernet 43 44 44 44 44 44 External Slave Peripheral Bus 47 External Slave Peripheral Bus External Slave Peripheral Bus 47 47 External Slave Peripheral Bus 47 Interface Group Page
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 16 of 17)
Signal Name TCK [TC0/EOT0]GPIO0_24 [TC1/EOT1]GPIO0_25 [TC2/EOT2]GPIO0_26 [TC3/EOT3]GPIO0_27 TDI TDO TestEn TmrClk TMS [TrcClk]GPIO0_31 TRST [TS1E]GPIO0_01 [TS2E]GPIO0_02 [TS1O]GPIO0_03 [TS2O]GPIO0_04 [TS3]GPIO0_05 [TS4]GPIO0_06 [TS5]GPIO0_07 [TS6]GPIO0_08 [UART0_CTS]GPIO1_26 [UART0_DCD]GPIO1_28 [UART0_DSR]GPIO1_27 [UART0_DTR]GPIO1_31 [UART0_RI]GPIO1_29 [UART0_RTS]GPIO1_30 UART0_Rx UART0_Tx [UART1_CTS]GPIO1_20[HDLCMPTxEn0] [UART1_DCD]GPIO1_22[HDLCMPTxEn2] [UART1_DSR]GPIO1_21[HDLCMPTxEn1] [UART1_DTR]GPIO1_25[HDLCMPTxEnB] [UART1_RI]GPIO1_23[HDLCMPTxEn3] [UART1_RTS]GPIO1_24[HDLCMPTxEnA] UART1_Rx UART1_Tx UARTSerClk Ball K33 AF34 AE32 AF33 AE31 N32 J34 M33 D32 H32 AH34 L34 U33 V33 V34 W34 W33 V32 Y33 Y32 E33 E34 F32 H31 F33 G32 AG32 AH33 D33 E32 C34 D34 F31 C33 AH32 AJ33 AG31 Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral 49 49 49 49 49 49 49 49 49 49 49 49 49 49 49 49 49 Trace 51 JTAG JTAG System System JTAG Trace JTAG Trace Trace 50 50 51 51 50 51 50 51 51 External Slave Peripheral Bus 47 JTAG Interface Group Page 50
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Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 17 of 17)
Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD WE Ball D13 D15 D16 D19 D20 D22 N04 N31 R04 R31 T04 T31 Power W04 W31 Y04 Y31 AB04 AB31 AL13 AL15 AL16 AL19 AL20 AL22 AM21 SDRAM 46 51 Interface Group Page
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Data Sheet
SIGNALS LISTED BY BALL ASSIGNMENT
Table 4. Signals Listed by Ball Assignment (Sheet 1 of 9)
Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in "Signals Listed Alphabetically" on page 15 for an indication of all signals on the pin.
Ball A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 GND GND PCIAD11 PCIAD13 PCIAD14 GND PCIPErr PCIDevSel PCIReq5 GND OVDD PCIAD19 PCIAD20 PCIIDSel GND PCIAD26 PCIGnt1 PCIAD31 PCIReq0 * GND PHY0CrS * EMC0TxErr * EMC0TxD3 * EMC0TxD0 * GND PHY0RxD2 * GPIO1_01 * GPIO1_04 * GND GPIO1_10 * GPIO1_13 * GPIO1_17 * GND GND Signal Name Ball B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 GND GND PCIAD10 PCIReq3 OVDD PCIC1[BE1] PCIParity PCIStop PCIIRDY PCIC2[BE2] PCIClk PCIAD18 PCIAD21 PCIAD23 PCIAD24 PCIAD25 PCIAD28 PCIAD30 PCIGnt0[Req] PCIReset EMC0MDIO OVDD EMC0TxD1 * PHY0RxClk PHY0RxD3 Signal Name Ball C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 Signal Name PCIAD08 PCIAD09 GND PCIAD12 PCIINT[PerWE] PCIAD15 PCIReq4 OVDD PCITRDY PCIFrame PCIAD16 PCIAD17 PCIGnt4 PCIAD22 PCIC3[BE3] OVDD PCIAD27 PCIAD29 PHY0TxClk * PHY0Col * EMC0MDClk EMC0TxD2 * PHY0RxDV * PHY0RxErr * PHY0RxD1 GPIO1_02 * GPIO1_05 * GPIO1_08 * GPIO1_11 * GPIO1_16 * GPIO1_19 * GND GPIO1_24 * GPIO1_21 * Ball D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 Signal Name PCIC0[BE0] PCIReq1 PCIAD07 GND OVDD PCIGnt2 OVDD PCISErr OVDD PCIGnt3 OVDD GND VDD PCIGnt5 VDD VDD GND GND VDD VDD EMC0TxEn * VDD GND OVDD GPIO1_00 * OVDD GPIO1_07 * OVDD GPIO1_15 * OVDD GND TmrClk GPIO1_20 * GPIO1_25 *
*
C25 C26 C27 C28 C29 C30 C31 C32 C33 C34
*
PHY0RxD0 * GPIO1_03 * GPIO1_06 * GPIO1_09 * GPIO1_12 * GPIO1_18 * GPIO1_14 *] GND GND
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Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 9)
Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in "Signals Listed Alphabetically" on page 15 for an indication of all signals on the pin.
Ball E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 Signal Name PCIAD06 PCIReq2 OVDD OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD GPIO1_22 * GPIO1_26 * GPIO1_28 *] Ball F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 A11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 GND PCIAD04 OVDD PCIAD05 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GPIO1_23 * GPIO1_27 * GPIO1_29 * GND Signal Name Ball G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 Signal Name PCIAD01 PCIAD02 PCIAD03 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD GPIO1_30 * HDLCMPRxClk0 HDLCMPRxData0 Ball H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 Signal Name HoldAck ExtAck BusReq PCIAD00 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GPIO1_31 * TMS HDLCMPRxClk1 HDLCMPRxClk2
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Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 3 of 9)
Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in "Signals Listed Alphabetically" on page 15 for an indication of all signals on the pin.
Ball J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 Signal Name PerErr HoldReq ExtReq OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD HDLCMPRxData1 SysReset TDO Ball K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 GND PerClk ExtReset HoldPri No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball HDLCMPRxData2 SysErr TCK GND Signal Name Ball L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 L34 Signal Name PerOE PerReady PerBLast OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD OVDD SysClk TRST Ball M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 Signal Name PerWBE2 PerCS0 PerR/W GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND OVDD TestEn OVDD
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 4 of 9)
Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in "Signals Listed Alphabetically" on page 15 for an indication of all signals on the pin.
Ball N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 N32 N33 N34 Signal Name PerAddr31 PerWBE0 PerWBE3 VDD No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball VDD TDI Halt HDLCMPRxClk3 Ball P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 Signal Name PerAddr27 PerAddr29 PerAddr30 PerWBE1 No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball AVDD HDLCMPRxData3 HDLCMPTxClk0 HDLCMPTxClk1 Ball R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 GND PerAddr25 PerAddr26 VDD No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball VDD HDLCMPTxData1 HDLCMPTxClk2 GND Signal Name Ball T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 Signal Name PerAddr22 PerAddr23 PerAddr28 VDD No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball VDD HDLCMPTxData0 HDLCMPTxClk3 HDLCMPTxData3
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Revision 1.01 - April 18, 2007
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 5 of 9)
Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in "Signals Listed Alphabetically" on page 15 for an indication of all signals on the pin.
Ball U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 Signal Name PerAddr21 PerAddr20 PerAddr24 GND No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball GND HDLCMPTxData2 GPIO0_01 * GPIO0_00 Ball V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 Signal Name PerAddr18 PerAddr19 PerAddr15 GND No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball GND GPIO0_06 * GPIO0_02 * GPIO0_03 * Ball W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W33 W34 Signal Name PerAddr17 PerAddr16 PerAddr11 VDD No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball VDD GPIO0_10 * GPIO0_05 * GPIO0_04 * Ball Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 GND PerAddr14 PerAddr13 VDD No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball VDD GPIO0_08 * GPIO0_07 * GND Signal Name
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 6 of 9)
Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in "Signals Listed Alphabetically" on page 15 for an indication of all signals on the pin.
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 Signal Name PerAddr12 PerAddr10 PerAddr09 PerAddr06 No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball GPIO0_15 * GPIO0_12 * GPIO0_11 * GPIO0_09 * Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34 Signal Name PerAddr08 PerAddr07 PerAddr04 VDD No ball No ball No ball No ball No ball No ball No ball No ball GND GND GND GND GND GND GND GND GND GND No ball No ball No ball No ball No ball No ball No ball No ball VDD GPIO0_17 * GPIO0_14 * GPIO0_13 * Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 Signal Name PerAddr05 PerAddr03 PerAddr01 GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND GPIO0_20 * GPIO0_18 * GPIO0_16 * Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 Signal Name PerAddr02 PerAddr00 PerPar3 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD GPIO0_22 * GPIO0_21 * GPIO0_19 *
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Revision 1.01 - April 18, 2007
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 7 of 9)
Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in "Signals Listed Alphabetically" on page 15 for an indication of all signals on the pin.
Ball AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 GND PerData31 PerData29 PerData27 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GPIO0_27 * GPIO0_25 * GPIO0_23 * GND Signal Name Ball AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 Signal Name PerData30 PerData28 PerData25 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD GPIO0_29 * GPIO0_26 * GPIO0_24 * Ball AG01 AG02 AG03 AG04 AG05 AG06 AG07 AG08 AG09 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 Signal Name PerData26 PerData24 PerData23 PerData21 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball UARTSerClk UART0_Rx GPIO0_30 * GPIO0_28 * Ball AH01 AH02 AH03 AH04 AH05 AH06 AH07 AH08 AH09 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 Signal Name PerPar2 PerData22 PerData20 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD UART1_Rx UART0_Tx GPIO0_31 *
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 8 of 9)
Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in "Signals Listed Alphabetically" on page 15 for an indication of all signals on the pin.
Ball AJ01 AJ02 AJ03 AJ04 AJ05 AJ06 AJ07 AJ08 AJ09 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 GND PerData19 PerData17 PerData14 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball HDLCEXRxClk IICSDA[IECSDA] UART1_Tx GND Signal Name Ball AK01 AK02 AK03 AK04 AK05 AK06 AK07 AK08 AK09 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 Signal Name PerData18 PerData16 PerData13 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD HDLCEXTxDataA HDLCEXRxDataA IICSCL[IECSCL] Ball AL01 AL02 AL03 AL04 AL05 AL06 AL07 AL08 AL09 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 Signal Name PerPar1 PerData11 PerData10 GND OVDD PerData06 OVDD MemData31 OVDD MemData24 OVDD GND VDD MemData15 VDD VDD GND GND VDD VDD BankSel0 VDD GND OVDD ECC7 OVDD OVDD OVDD MemAddr10 OVDD GND HDLCEXTxClk HDLCEXTxFS HDLCEXRxDataB Ball AM01 AM02 AM03 AM04 AM05 AM06 AM07 AM08 AM09 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 Signal Name PerData12 PerData15 GND PerData09 PerData07 OVDD PerData00 MemData29 MemData26 MemData23 OVDD MemData19 MemData16 MemData12 MemData08 MemData10 GND MemData00 OVDD DQMCB WE BankSel2 OVDD ECC2 ECC5 MemAddr01 MemClkOut0 MemAddr04 MemAddr07 MemAddr11 BA1 GND HDLCEXRxFS HDLCEXTxDataB
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DS2011
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 9 of 9)
Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in "Signals Listed Alphabetically" on page 15 for an indication of all signals on the pin.
Ball AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 GND GND PerData05 PerData08 PerData03 PerData01 MemData30 MemData27 DQM3 MemData21 MemData20 MemData17 MemData14 MemData11 DQM1 MemData07 MemData05 MemData04 MemData01 DQM0 ClkEn1 CAS BankSel3 ECC1 ECC3 ECC6 MemAddr02 MemAddr03 MemAddr05 MemAddr08 BA0 OVDD GND GND Signal Name Ball AP01 AP02 AP03 AP04 AP05 AP06 AP07 AP08 AP09 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 GND GND PerPar0 PerData04 PerData02 GND MemData28 MemData25 MemData22 GND MemData18 DQM2 MemData13 MemData09 GND MemData06 OVDD MemData03 MemData02 GND ClkEn0 RAS BankSel1 ECC0 GND ECC4 MemAddr00 MemClkOut1 GND MemAddr06 MemAddr09 MemAddr12 GND GND Signal Name Ball Signal Name Ball Signal Name
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
SIGNAL DESCRIPTION
The following table provides a summary of the number of package pins (balls) associated with each functional interface group.
PIN SUMMARY
Table 5. Pin Summary
Group
Nonmultiplexed Signals Multiplexed Signals Total Signal Pins AVDD OVDD VDD Gnd Gnd (and thermal) Reserved Total Pins
No. of Pins
256 85 341 1 49 24 65 100 0 580
Multiplexed Pins In the table "Signal Functional Description" on page 43, each external signal is listed along with a short description of the signal function. The signals are grouped together according to their function. Some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. In most cases, the signal name is shown in this table unaccompanied by multiplexed signal names that may be associated with it. In cases where multiplexed signals are in the same functional group, the names appear as a default signal followed by secondary signals in square brackets (for example, EMC0TxErr[EMC0Tx1En]). Active-low signals (for example, RAS) are marked with an overline. Any signal that is not the primary (default) signal on a multiplexed pin is shown in square brackets. The active signal on a multiplexed pin is controlled by programming. It is expected that in any single application, a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. Multipurpose Pins In addition to multiplexing, pins may also be multipurpose. An example of multi-purpose use occurs when the EBC peripheral controller address pins are used as outputs by the NPe405H to broadcast an address to external slave devices when the NPe405H has control of the external bus. However, when an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the NPe405H. In this example, the pins are also bidirectional, serving as both inputs and outputs. Initialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Initialization" on page 68). Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Pull-up and Pull-down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3k to +3.3V (10k to +5V can be used on 5V tolerant I/Os) and pull-down value of 1k to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor. If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the NPe405H. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the NPe405H requires only the pull-up and pull-down terminations as specified in the "Signal Functional Description" on page 43, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM, and PCI buses should be configured and terminated as follows: * * * Peripheral interface--PerAddr00:31, PerData00:31, and all of the control signals are driven by default. Terminate PerReady high and PerError low. SDRAM--Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the NPe405H to actively drive all of the SDRAM address, data, and control signals. PCI--Configure the PCI controller to park on the bus and actively drive PCIAD31:0, PCIC3:0[BE3:0], and the remaining PCI control signals by doing the following: - Strap the NPe405H to disable the internal PCI arbiter. - Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3k resistors to +3.3V. - Terminate PCIReq1:5 to +3.3V. - Terminate PCIReq0[Gnt] to GND.
External Peripheral Bus Control Signals All external peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerNP NPe405H Embedded Processor User's Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions or when an external master owns the peripheral bus. As a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the NPe405H. Please see "Signals Listed Alphabetically" on page 15 for the pin number to which each signal is assigned. In cases where a multiplexed signal (indicated by the square brackets) is shown without the other signals that are assigned to that pin, you can see what the other signals are by referring to the same table.
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NPe405H - PowerNP NPe405H Embedded Processor
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Data Sheet
SIGNAL FUNCTIONAL DESCRIPTION
Table 6. Signal Functional Description (Sheet 1 of 9)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 42.
Signal Name Description I/O Type
Notes
PCI Interface
PCIAD0:31 PCIC3:0[BE3:0] PCI Address/Data bus. Multiplexed address and data bus PCI bus command or Byte Enable PCI Parity. Parity is even across PCIAD0:31 and PCIC0:3[BE0:3]. PCIParity is valid one cycle after either an address or data phase. The PCI device that drove PCIAD0:31 is responsible for driving PCIParity on the next PCI bus clock. Driven by the current PCI bus master to indicate the beginning and duration of a PCI access. Driven by the current PCI bus master. Assertion of PCIIRDY indicates that the PCI initiator is ready to transfer data. The target of the current PCI transaction drives PCITRDY. Assertion of PCITRDY indicates that the PCI target is ready to transfer data. The target of the current PCI transaction can assert PCIStop to indicate to the requesting PCI master that it wants to end the current transaction. Driven by the target of the current PCI transaction. A PCI target asserts PCIDevSel when it has decoded an address and command encoding and claims the transaction. Used during configuration cycles to select the PCI slave interface for configuration Used for reporting address parity errors or catastrophic failures detected by a PCI target. Used for reporting data parity errors on PCI transactions. PCIPErr is driven active by the device receiving PCIAD0:31, PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the data in which bad parity is detected. Used as the asynchronous PCI clock. PCI specific reset PCI Interrupt. Open-drain output (two states; 0 or open circuit). Req0 when internal arbiter is used, or Gnt when external arbiter is used. IF PCI bus is used, pull this signal up; otherwise, pull down. Used as PCIReq1:5 input when internal arbiter is used Gnt0 when internal arbiter is used, or Req when external arbiter is used I/O I/O 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 4
PCIParity
I/O
PCIFrame PCIIRDY
I/O I/O
4 4
PCITRDY
I/O
4
PCIStop
I/O
4
PCIDevSel
I/O
4
PCIIDSel PCISErr
I I/O
5 4
PCIPErr
I/O
4
PCIClk PCIReset PCIINT
I O O
PCIReq0[Gnt]
I
PCIReq1:5 PCIGnt0[Req]
I O
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Revision 1.01 - April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 9)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 42.
Signal Name PCIGnt1:5 Description PCIGnt1:5 output when internal arbiter is used. I/O O Type 5V tolerant 3.3V PCI
Notes
HDLCEX Interface
HDLCEXTxClk HDLCEXTxFS HDLCEXTxDataA HDLCEXTxDataB HDLCEXRxClk HDLCEXRxFS HDLCEXRxDataA HDLCEXRxDataB [HDLCEXTxEnA] [HDLCEXTxEnB] Transmit Clock Transmit Frame Synchronization Transmit Data port A Transmit Data port B Receive Clock Receive Frame Synchronization Receive Data port A Receive Data port B Transmit Enable port A Transmit Enable port B I I O O I I I I O O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
HDLCMP Interface
HDLCMPTxClk0:3 [HDLCMPTxClk4:7] HDLCMPTxData0:3 [HDLCMPTxData4:7] [HDLCMPTxEn0:7] HDLCMPRxClk0:3 [HDLCMPRxClk4:7] HDLCMPRxData0:3 [HDLCMPRxData4:7] Transmit Clock signal that controls the transmit bit rate Transmit Clock signal that controls the transmit bit rate Transmit Data signal Transmit Data signal Transmit Data Enable signal that controls when the external buffer is tri-stated Receive Clock signal that controls the receive bit rate Receive Clock signal that controls the receive bit rate Receive Data signal Receive Data signal O O O O O I I I I 3.3V LVTTL 5V tolerant 3.3V LVTTL 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 3.3V LVTTL 5V tolerant 3.3V LVTTL 3.3V LVTTL 5V tolerant 3.3V LVTTL
Ethernet Interface
EMC0MDClk Management Data Clock. The MDClk is sourced to the PHY. Management information is transferred synchronously with respect to this clock (MII, RMII, and SMII). Management Data Input/Output is a bidirectional signal between the Ethernet controller and the PHY. It is used to transfer control and status information (MII, RMII, and SMII). O 3.3V LVTTL
EMC0MDIO
I/O
5V tolerant 3.3V LVTTL
1, 4
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 9)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 42.
Signal Name Description I/O Type
Notes
EMC0TxD0[EMC0Tx0D0][EMC0Tx0D] Transmit Data. A nibble wide data bus towards the net. The EMC0TxD1[EMC0Tx0D1][EMC0Tx1D] data is synchronous with PHY0TxClk (MII 0[RMII 0, 1][SMII 0, EMC0TxD2[EMC0Tx1D0][EMC0Tx2D] 1, 2, 3]). EMC0TxD3[EMC0Tx1D1][EMC0Tx3D] [EMC1TxD0][EMC1Tx2D0] [EMC1TxD1][EMC1Tx2D1] [EMC1TxD2][EMC1Tx3D0] [EMC1TxD3][EMC1Tx3D1]
O
3.3V LVTTL
RMII Transmit Data (MII 1[RMII 2, 3]).
O
5V tolerant 3.3V LVTTL
EMC0TxEn[EMC0Tx0En][EMC0Sync]
Transmit Enable. This signal is driven by EMAC2 to the PHY. Data is valid during the active state of this signal. Deassertion of this signal indicates end of frame transmission. This signal is synchronous with PHYTxClk (MII 0[RMII 0]). or SMII Sync. Transmit Error. This signal is generated by the Ethernet controller, is connected to the PHY and is synchronous with the PHY0TxClk. It informs the PHY that an error was detected (MII 0). or Transmit Enable [RMII 1]. Transmit Enable ([MII 1][RMII 2]). Transmit Error. This signal is generated by the Ethernet controller, is connected to the PHY and is synchronous with the PHY1TxClk. It informs the PHY that an error was detected ([MII 1]). or Transmit Enable [RMII 3]. Collision [receive error] signal from the PHY. This is an asynchronous signal (MII 0). or Receive Error ([RMII 1]). Carrier Sense signal from the PHY. This is an asynchronous signal (MII 0). or Carrier sense data valid ([RMII 0]). Receiver medium clock. This signal is generated by the PHY (MII 0). Received Data. This is a nibble wide bus from the PHY. The data is synchronous with PHY0RxClk (MII 0[RMII 0, 1][SMII 0, 1, 2, 3]).
O
3.3V LVTTL
EMC0TxErr[EMC0Tx1En]
O
3.3V LVTTL
[EMC1TxEn][EMC1Tx2En]
O
5V tolerant 3.3V LVTTL
[EMC1TxErr][EMC1Tx3En]
O
5V tolerant 3.3V LVTTL
PHY0Col[PHY0Rx1Er]l
I
5V tolerant 3.3V LVTTL
PHY0CrS[PHY0CrS0DV]
I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1, 5
PHY0RxClk PHY0RxD0[PHY0Rx0D0][PHY0Rx0D] PHY0RxD1[PHY0Rx0D1][PHY0Rx1D] PHY0RxD2[PHY0Rx1D0][PHY0Rx2D] PHY0RxD3[PHY0Rx1D1][PHY0Rx3D] [PHY1RxD0][PHY1Rx2D0] [PHY1RxD1][PHY1Rx2D1] [PHY1RxD2][PHY1Rx3D0] [PHY1RxD3][PHY1Rx3D1]
I
1, 4
I
1, 4
Receive Data (MII 1[RMII 2, 3]).
I
5V tolerant 3.3V LVTTL
AMCC Proprietary
DS2011
45
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 9)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 42.
Signal Name Description Receive Data Valid. Data on the Data Bus is valid when this signal is activated. Deassertion of this signal indicates end of the frame reception (MII 0). or Carrier sense data valid ([RMII 1]) Receive Error. This signal comes from the PHY and is synchronous with PHY0RxClk (MII 0 [RMII 0]). Transmit medium clock. This signal is generated the PHY ([MII 0]). or Reference Clock [RMII and SMII]. Collision [receive error] signal from the PHY. This is an asynchronous signal ([MII 1]). or Receive Error. This signal comes from the PHY and is synchronous with PHY1RxClk ([RMII 3]). Carrier Sense signal from the PHY. This is an asynchronous signal ([MII 1]). or Carrier Sense Data Valid ([RMII 2]). Receiver medium clock. This signal is generated by the PHY ([MII 1]). Receive Data Valid ([MII 1]). or Carrier Sense Data Valid ([RMII 3]). Receive Error. This signal comes from the PHY and is synchronous with PHY1RxClk ([MII 1][RMII 2]). Transmit medium clock. This signal is generated the PHY ([MII 1]). I/O Type
Notes
PHY0RxDV[PHY0CrS1DV]
I
5V tolerant 3.3V LVTTL
1, 5
PHY0RxErr[PHY0Rx0Er]
I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1, 5
PHY0TxClk[PHY0RefClk]
I
1, 4
[PHY1Col][PHY1Rx3Er]
I
5V tolerant 3.3V LVTTL
1, 5
[PHY1CrS][PHY1CrS2DV]
I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 4
[PHY1RxClk]
I
1, 4
[PHY1RxDV][PHY1CrS3DV]
i
[PHY1RxErr][PHY1Rx2Er] [PHY1TxClk] SDRAM Interface
I I
MemAddr00:31
Memory Data bus Notes: 1. MemAddr00 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb). Memory Address bus. Notes: 1. MemAddr12 is the most significant bit (msb). 2. MemAddr00 is the least significant bit (lsb). Bank Address supporting up to 4 internal banks Row Address Strobe. Column Address Strobe. DQM for byte lane 0 (MemAddr00:7), 1 (MemAddr08:15), 2 (MemData16:23), and 3 (MemData24:31)
I/O
3.3V LVTTL
MemAddr12:00
O
3.3V LVTTL
BA1:0 RAS CAS
O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
O
3.3V LVTTL
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DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 9)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 42.
Signal Name DQMCB ECC0:7 BankSel0:3 WE ClkEn0:1 MemClkOut0:1 External Slave Peripheral Bus Interface PerData00:31 External peripheral data bus when not in external master mode, otherwise used by external master. Note: PerData00 is the most significant bit (msb) on this bus. External peripheral address bus when not in external master mode, otherwise used by external master. External peripheral byte parity signals. Peripheral write-bte enable. Byte-enables which are valid for an entire cycle or write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. Used by either external bus controller or DMA controller depending upon the type of transfer involved. Used as inputs when external bus master owns the external interface. Peripheral write enable. Low when any of the four PerWBE signals are low. Peripheral Chip Selects Peripheral output enable. Used by either the external bus controller or the DMA controller depending upon the type of transfer involved. When the NPe405H is the bus master, it enables the peripherals to drive the bus. Peripheral read/write. Used when not in external master mode by either the external bus controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise it used by the external master as an input to indicate the direction of transfer. Indicates peripheral is ready to transfer data. Peripheral burst last. Used to indicate the last transfer of a memory access. Peripheral Clock. Used by an external master and by synchronous peripheral slaves. Used to indicate errors from peripherals. I/O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1 Description DQM for ECC check bits. ECC check bits 0:7. Select up to four external SDRAM banks. Write Enable. SDRAM Clock Enable. Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attachment without requiring this signal to be repowered by a PLL or zero-delay buffer. I/O O I/O O O O O Type 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Notes
PerAddr00:31 PerPar0:3
I/O I/O
1 1
PerWBE0:3
I/O
5V tolerant 3.3V LVTTL
1, 2, 7
[PerWE] PerCS0 [PerCS1:7]
I/O O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
7
PerOE
O
7
PerR/W
I/O
5V tolerant 3.3V LVTTL
1
PerReady PerBLast PerClk PerErr
I I/O O I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1 1, 7
1, 5
AMCC Proprietary
DS2011
47
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 9)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 42.
Signal Name Description DMA request. Used by peripheral slaves to request a data transfer. Following a system reset, the default mode of the signals is active-low. They may be programmed to active-high using the DMA0_POL register. DMA acknowledge. Used to indicate to peripherals that data transfer is complete. Following a system reset, the default mode of the signals is active-low. They may be programmed to active-high using the DMA0_POL register. End Of Transfer/Terminal Count. Indication by peripherals that all data has been transferred, or by DMA controller that programmed amount of data has been transferred. Following a system reset, the default mode of the signals is active-low. They may be programmed to active-high using the DMA0_POL register. I/O Type 5V tolerant 3.3V LVTTL
Notes
1
[DMAReq0:3]
I
[DMAAck0:3]
O
5V tolerant 3.3V LVTTL
[EOT0:3/TC0:3]
I/O
5V tolerant 3.3V LVTTL
1
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DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 7 of 9)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 42.
Signal Name External Master Peripheral Interface ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq Internal Peripheral Interface Serial Clock used to provide an alternative clock to the internally generated serial clock. Used in cases where the allowable internally generated baud rates are not satisfactory. This input can be individually connected to either or both UART0 and UART1. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Set Ready. UART0 Clear To Send. UART0 Data Terminal Ready. UART0 Request To Send. UART0 Ring Indicator. Peripheral Reset. Used by an external master and synchronous peripheral slaves. Hold Request. Used by an external master to request ownership of the peripheral bus. Hold Acknowledge. Used by the NPe405H to transfer ownership of peripheral bus to an external master. External Request. Used by an external master to indicate it is prepared to transfer data. External Acknowledgement. Used by the NPe405H to indicate that a data transfer occurred. Hold Primary. Used by an external master to indicate the priority of a given transfer (0 = high, 1 = low). Bus Request. Used when the NPe405H needs to regain control of peripheral interface from an external Master. O I O I O I O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 5 6 1 6 1 Description I/O Type
Notes
UARTSerClk
I
5V tolerant 3.3V LVTTL
1
UART0_Rx UART0_Tx [UART0_DCD] [UART0_DSR] [UART0_CTS] [UART0_DTR] [UART0_RTS] [UART0_RI]
I O I I I O O I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL r
1
1 1 1
1
AMCC Proprietary
DS2011
49
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 8 of 9)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 42.
Signal Name UART1_Rx UART1_Tx [UART1_DCD] [UART1_DSR] [UART1_CTS] [UART1_DTR] [UART1_RTS] [UART1_RI] IICSCL[IECSCL] IICSDA[IECSDA] Interrupts Interface [IRQ0:6] JTAG Interface TDI TMS TDO TCK TRST Test Data In. Test Mode Select. Test Data Out. Test Clock. Test Reset. TRST must be low at power-on to reset the JTAG boundary scan state machine. I I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 4 5 1, 4 1, 4 Interrupt Requests. I 5V tolerant 3.3V LVTTL 1 UART1 Receive data. UART1 Transmit data. UART1 Data Carrier Detect. UART1 Data Set Ready. UART1 Clear To Send. UART1 Data Terminal Ready. UART1 Request To Send. UART1 Ring Indicator. IIC [Initilization PROM] Serial Clock. IIC [Initilization PROM] Serial Data. Description I/O I O I I I O O I I/O I/O Type 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 4 1, 2 1, 2
Notes
1 6 1, 4 1, 4 1, 4
50
DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 9 of 9)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 42 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 42.
Signal Name System Interface SysClk SysReset SysErr Halt GPIO0_00:31 GPIO1_00:31 TestEn Main System Clock input. Main System Reset. Set to 1 when a Machine Check is generated. Halt from external debugger. System General Purpose I/O. Communications General Purpose I/O. Test Enable. Used only for manufacturing tests. Pull down for normal operation. This input must toggle at a rate of less than one half the CPU core frequency (less than 100MHz in most cases). In most cases this input toggles much slower (in the 1MHz to 10MHz range). I I/O O I I/O I/O I 3.3V Analog Wire w/ESD 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 3.3V LVTTL Rcvr w/PD 5V tolerant 3.3V LVTTL 1 1, 2 Description I/O Type
Notes
TmrClk
I
1
Trace Interface [TS1E] [TS2E] [TS1O] [TS2O] [TS3:6] Even Trace execution status.To access this function, software must toggle a DCR bit. Odd Trace execution status. To access this function, software must toggle a DCR bit. Trace Status. To access this function, software must toggle a DCR bit. Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR bit. O O O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
[TrcClk] Power Pins GND VDD OVDD AVDD Other Pins Reserved
O
Ground Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14, and P09-P14 are also thermal balls. Logic voltage--2.5V Output driver voltage--3.3V Filtered PLL voltage--2.5V
I I I I
Hardwire Hardwire Hardwire 3.3V DC Wire w/ESD
Do not connect signals, voltage, or ground to these pins.
n/a
n/a
AMCC Proprietary
DS2011
51
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) PLL Supply Voltage 2 Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias
Notes: 1. All voltages are specified with respect to ground (GND). 2. AVDD should be derived from VDD using the following circuit:
Symbol VDD OVDD AVDD VIN VIN TSTG TC
Value 0 to +2.7 0 to +3.6 0 to +2.7 -0.6 to (OVDD + 0.6) -0.6 to (OVDD + 2.4) -55 to +150 -40 to +120
Unit V V V V V xC xC
VDD L1
AVDD L1 - 2.2H SMT inductor (equivalent to MuRata LQH3C2R2M34) or SMT chip ferrite bead (equivalent to MuRata BLM31A700S)
C1
C2
C3
C1 - 3.3 F SMT tantalum C2 - 0.1F SMT monolithic ceramic capacitor with X7R dielectric or equivalent C3 - 0.01 F SMT monolithic ceramic capacitor with X7R dielectric or equivalent
PACKAGE THERMAL SPECIFICATIONS
Table 8. Package Thermal Specifications
The NPe405H is designed to operate within a case temperature range of -40C to 85C. Thermal resistance values for the EPBGA packages in a convection environment are as follows:
Package--Thermal Resistance
35mm, 580-balls--Junction-to-Case 1 35mm, 580-balls--Case-to-Ambient
Symbol 0 (0)
Airflow ft/min (m/sec)
100 (0.51) 2 12 200 (1.02) 2 11 2 13
Unit
C/W C/W
JC CA
Notes:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. c. TCMax = TJMax - PxJC, where TJMax is maximum junction temperature and P is power consumption.
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DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
RECOMMENDED DC OPERATING CONDITIONS
Table 9. Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications.
Parameter Logic Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Logic High (3.3V LVTTL receivers) Input Logic High (2.5V CMOS receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Low Output Logic High Output Logic Low 3.3V I/O input current (no pull-up or pull-down) Input Current (with internal pull-down) Input Current (with internal pull-up) Input Max Allowable Overshoot (2.5V CMOS receivers) Input Max Allowable Overshoot (3.3V LVTTL receivers) Input Max Allowable Overshoot (5.0V LVTTL receivers) Input Max Allowable Undershoot (3.3V or 5.0V receivers) Output Max Allowable Overshoot (3.3V or 5.0V receivers) Output Max Allowable Undershoot (3.3V and 5.0V receivers) Case Temperature
Notes: 1. See "" on page 54
Symbol VDD OVDD AVDD VIH VIH VIH VIL VOH VOL IIL1 IIL2 IIL3 VIMAO25 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3 TC
Minimum +2.3 +3.0 +2.3 +2.0 +1.7 +2.0 0 +2.4 0
Typical +2.5 +3.3 +2.5
Maximum +2.7 +3.6 +2.7 OVDD VDD +5.5 +0.8 OVDD +0.4 10
Unit V V V V V V V V V
Notes
A A A
V V V V
10 (@ 0V) -250 (@ 0V)
400 (@ 3.6V) 10 (@ 3.6V) VDD + 0.6 OVDD + 0.6 +5.5
- 0.6
OVDD + 0.3
V V
- 0.6 - 40
+85
xC
AMCC Proprietary
DS2011
53
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
5 V-TOLERANT I/O INPUT CURRENT
Figure 3. 5V-Tolerant I/O Input Current
100 0 -100 Input Current (A) -200 -300 -400 -500 -600 -700 0.0 1.0 2.0 3.0 4.0 5.0 Input Voltage (V)
INPUT CAPACITANCE
Table 10. Input Capacitance
Parameter 3.3V LVTTL I/O) 5V tolerant LVTTL I/O PCI I/O RX only pins Symbol CIN1 CIN2 CIN3 CIN4 Maximum 2.5 3.5 5.0 0.75 Unit pF pF pF pF Notes
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DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
DC ELECTRICAL CHARACTERISTICS
Table 11. DC Electrical Characteristics
Parameter Active Operating Current for VDD @ 133MHz Active Operating Current for VDD @ 200MHz Active Operating Current for VDD @ 266MHz Active Operating Current for OVDD @ 133MHz Active Operating Current for OVDD @ 200MHz Active Operating Current for OVDD @ 266MHz Active Operating Current for AVDD Active Operating Power @ 133MHz Active Operating Power @ 200MHz Active Operating Power @ 266MHz Symbol IDD IDD IDD IODD IODD IODD IADD PDD PDD PDD Minimum 599 755 964 77 89 97 5.5 1.6 2 2.5 Typical 669 843 1074 89 102 111 6 2 2.4 3 Maximum 740 928 1183 99 112 123 6.5 2.4 1 Unit mA mA mA mA mA mA mA W W W
2.91 3.6 1
Notes: 1. Maximum power is characterized at VDD=2.7V, OVDD=3.6V, TC=85xC, across the silicon process (worse case to best case), while running an application designed to maximize power consumption. The maximum power values are measured with the following clock rate combinations: a. CPU=133.33MHz, PLB=66.66MHz, OPB=66.66MHz, EBC=33.33MHz, PCI=33.33MHz b. CPU=200 MHz, PLB=100MHz, OPB=50MHz, EBC=50MHz, PCI=33.33MHz c. CPU=266.66MHz, PLB=133.33MHz, OPB=66.66MHz, EBC=66.66MHz, PCI=33.33MHz
TEST CONDITIONS
Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table "Recommended DC Operating Conditions." AC specifications are characterized at OVDD = 3.00V and TJ = 85C with the 50pF test load shown in the figure at right.
Output Pin 50pF
AMCC Proprietary
DS2011
55
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
CLOCKING SPECIFICATIONS
Table 12. Clocking Specifications
Symbol SysClk Input FC TC TCS TCH TCL SysClk clock input frequency SysClk clock period Clock edge stability (phase jitter, cycle to cycle) Clock input high time Clock input low time 40% of nominal period 40% of nominal period 25 15 66.66 40 0.15 60% of nominal period 60% of nominal period MHz ns ns ns ns Parameter Min Max Units
Note:Input slew rate > 2V/ns
MemClkOut Output FC TC FC TC FC TC TCH TCL Other Clocks FC FC FC FC FC FC FC VCO frequency PLB frequency-133MHz PLB frequency-200MHz PLB frequency-266MHz OPB frequency-133MHz OPB frequency-200MHz OPB frequency-266MHz 400 800 66.66 100 133.33 50
1
MemClkOut clock output frequency-133MHz MemClkOut clock period-133MHz MemClkOut clock output frequency-200MHz MemClkOut clock period-200MHz MemClkOut clock output frequency-266MHz MemClkOut clock period-266MHz Clock output high time Clock output low time 7.5 45% of nominal period 45% of nominal period 10 15
66.66
MHz ns
100
MHz ns
133.33
MHz ns
55% of nominal period 55% of nominal period
ns ns
MHz MHz MHz MHz MHz MHz MHz
50 501
Notes: 1. If HDLCEX is not used, the maximum OPB frequency is 66.66MHz.
CLOCKING WAVEFORM
Figure 4. Clocking Waveform
2.0V 1.5V 0.8V TCH TC TCL
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DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
SPREAD SPECTRUM CLOCKING
Care must be taken when using a spread spectrum clock generator (SSCG) with the NPe405H. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the NPe405H the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the NPe405H with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. The maximum frequency deviation cannot exceed -3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board NPe405H peripherals impose more stringent requirements (see Note 1). Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation. Use the SDRAM MemClkOut since it also tracks the modulation.
* * *
Please refer to the application note Using a Spread Spectrum Clock Generator with the PowerPC 405GP for additional details. This application note is available on the AMCC web site at http://www.amcc.com. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaffected by the modulation. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected. 4. The PCI clock specification for 66MHz allows a maximum frequency deviation of -1% at a modulation between 30kHz and 33kHz. PCI asynchronous mode is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the NPe405H meets the above requirements and does not adversely affect other aspects of the system.
AMCC Proprietary
DS2011
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
PERIPHERAL INTERFACE CLOCK TIMINGS
Table 13. Peripheral Interface Clock Timings
Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk input high time PCIClk input low time EMC0MDClk output frequency EMC0MDClk period EMC0MDClk output high time EMC0MDClk output low time PHY0TxClk input frequency PHY0TxClk period PHY0TxClk input high time PHY0TxClk input low time PHY0RxClk input frequency PHY0RxClk period PHY0RxClk input high time PHY0RxClk input low time PerClk output frequency-133MHz PerClk period-133MHz PerClk output frequency-200MHz PerClk period-200MHz PerClk output frequency-266MHz) PerClk period-266MHz PerClk output high time PerClk output low time UARTSerClk input frequency (Note 1) UARTSerClk period UARTSerClk input high time UARTSerClk input low time TmrClk input frequency-133MHz TmrClk period-133MHz TmrClk input frequency-200MHz TmrClk period-200MHz TmrClk input frequency-266MHz TmrClk period-266MHz TmrClk input high time TmrClk input low time HDLCEXTxClk, HDLCEXRxClk HDLCMPTxClk, HDLCMPRxClk Min Note 2 15 40% of nominal period 40% of nominal period - 400 160 160 2.5 40 35% of nominal period 35% of nominal period 2.5 40 35% of nominal period 35% of nominal period - 30 - 20 - 15 45% of nominal period 45% of nominal period - 2TOPB + 2 TOPB + 1 TOPB + 1 - 30 - 20 - 15 40% of nominal period 40% of nominal period 0 - Max 66 Note 2 60% of nominal period 60% of nominal period 2.5 - - - 25 400 - - 25 400 - - 33.33 - 50 - 66.66 - 55% of nominal period 55% of nominal period 1000/(2TOPB + 2ns) - - - 33.33 - 50 - 66.66 - 60% of nominal period 60% of nominal period 8.192 2.048 Units MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns MHz ns MHz ns ns ns MHz ns ns ns MHz ns MHz ns MHz ns ns ns MHz MHz
Notes: 1. TOPB is the period in ns of the OPB clock. The maximum OPB clock frequency is 33.33 MHz for 133MHz parts, 50 MHz for 200MHz parts, and 66.66MHz for 266MHz parts. 2. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the NPe405H User's Manual for more information.
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
INPUT SETUP AND HOLD WAVEFORM
Figure 5. Input Setup and Hold Waveform
Clock
TIS min Inputs Valid
TIH min
OUTPUT DELAY AND FLOAT TIMING WAVEFORM
Figure 6. Output Delay and Float Timing Waveform
Clock
TOV max Outputs TOH min
TOV max TOH min
TOV max TOH min
High (Drive) Float (High-Z) Low (Drive) Valid Valid
AMCC Proprietary
DS2011
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Revision 1.01 - April 18, 2007
Data Sheet
I/O SPECIFICATIONS--ALL
Table 14. I/O Specifications--All (Sheet 1 of 2)
Notes: 1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for 33MHz.
Input (ns) Signal Setup Time (TIS min) 3.0 3.0 n/a 3.0 3.0 n/a 3.0 n/a 3.0 3.0 3.0 5.0 n/a 3.0 3.0 3.0 async async async async async n/a async n/a async n/a async async async n/a async n/a async n/a async async Hold Time (TIH min) 0.0 0.0 n/a 0.0 0.0 n/a 0.0 n/a 0.0 0.0 0.0 0.0 n/a 0.0 0.0 0.0 async async async async async n/a async n/a async n/a async async async n/a async n/a async n/a async async Output (ns) Valid Delay (TOV max) 6.0 6.0 n/a 6.0 6.0 6.0 n/a 6.0 6.0 6.0 6.0 n/a 6.0 6.0 6.0 6.0 async async n/a n/a n/a async n/a async n/a async n/a n/a n/a async n/a async n/a async n/a n/a Hold Time (TOH min) 2.0 2.0 n/a 2.0 2.0 2.0 n/a 2.0 2.0 2.0 2.0 n/a 2.0 2.0 2.0 2.0 async async n/a n/a n/a async n/a async n/a async n/a n/a n/a async n/a async n/a async n/a n/a Output Current (mA) I/O H (maximum) 0.5 0.5 n/a 0.5 0.5 0.5 n/a 0.5 0.5 0.5 0.5 n/a 0.5 0.5 0.5 0.5 17 17 n/a n/a n/a 12 n/a 12 n/a 12 n/a n/a n/a 12 n/a 12 n/a 12 n/a n/a I/O L (minimum) 1.5 1.5 n/a 1.5 1.5 1.5 n/a 1.5 1.5 1.5 1.5 n/a 1.5 1.5 1.5 1.5 11 11 n/a n/a n/a 8 n/a 8 n/a 8 n/a n/a n/a 8 n/a 8 n/a 8 n/a n/a PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk 6 6 Clock Notes
PCI Interface
PCIAD00:31 PCIC0:3[BE3:0] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1:5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1:5 PCIReset PCISErr PCIStop PCITRDY PCIClk PCIClk 6 6 async 6 6 6 6 async 6 6 6 6
Internal Peripheral Interface
IICSCL IICSDA [UART0_CTS] [UART0_DCD] [UART0_DSR] [UART0_DTR] [UART0_RI] [UART0_RTS] UART0_Rx UART0_Tx [UART1_CTS] [UART1_DCD] [UART1_DSR] [UART1_DTR] [UART1_RI] [UART1_RTS] UART1_Rx UART1_Tx UARTSerClk
Interrupts Interface
[IRQ0:6]
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DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 14. I/O Specifications--All (Sheet 2 of 2)
Notes: 1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for 33MHz.
Input (ns) Signal JTAG Interface TCK TDI TDO TMS TRST async async n/a async async na async n/a n/a n/a dc n/a async async n/a async async na async n/a n/a n/a dc n/a n/a n/a async n/a n/a na n/a n/a 8.6 7.4 n/a async n/a n/a async n/a n/a na n/a n/a 3.7 3.3 n/a async n/a n/a 12 n/a n/a 12 n/a n/a 12 12 n/a n/a n/a n/a 8 n/a n/a 8 n/a n/a 8 8 n/a n/a Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (maximum) I/O L (minimum) Clock Notes
System Interface
GPIO0:1 Halt SysClk SysErr SysReset TestEn TmrClk
AMCC Proprietary
DS2011
61
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
I/O SPECIFICATIONS(A)--133 AND 200 MHZ
Table 15. I/O Specifications--133 and 200MHz (Sheet 1 of 3)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal Ethernet Interface EMC0MDClk EMC0MDIO EMC0TxD0:3 [EMC0Tx0:1D0:1] [EMC0Tx0:3D] EMC0TxEn [EMC0Tx0En] [EMC0Sync] EMC0TxErr[EMC0Tx1En] [EMC1TxD0][EMC1Tx2D0] [EMC1TxD1][EMC1Tx2D1] [EMC1TxD2][EMC1Tx3D0] [EMC1TxD3][EMC1Tx3D1] [EMC1TxEn][EMC1Tx2En] [EMC1TxErr][EMC1Tx3En] PHY0Col[PHY0Rx1Er] PHY0CrS[PHY0CrS0DV] PHY0RxClk PHY0RxD0:3 [PHY0Rx0:1D0:1] [PHY0Rx0:3D] PHY0RxDV[PHY0CRS1DV] PHY0RxErr[PHY0Rx0Er] PHY0TxClk[PHY0RefClk] [PHY1RxD0][PHY1Rx2D0] [PHY1RxD1][PHY1Rx2D1] [PHY1RxD2][PHY1Rx3D0] [PHY1RxD3][PHY1Rx3D1] [PHY1Col][PHY1Rx3Er] [PHY1CrS][PHY1CrS2DV] [PHY1RxClk] [PHY1RxDV] [PHY1CrS3DV] [PHY1RxErr][PHY1Rx2Er] [PHY1TxClk] HDLCEX Interface HDLCEXRxClk HDLCEXRxDataA:B HDLCEXRxFS n/a 27.7 24.2 n/a 1.4 0.6 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 100 n/a n/a 0.0 n/a n/a n/a 12 12 12 8 8 8 EMC0MDClk PHYTX 1, async 1 1 1 OPB clock 1 OPB Clock period + 10ns period 12.4 7.0 5.0 14.4 7.0 5.0 13.6[7.1] [15.0][8.2] [15.0][8.3] [15.1][8.2] [15.0][8.2] [16.4][8.2] [16.5][8.3] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 4.1 2.3 1.5 4.3 2.3 1.5 4.0[2.4] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (maximum) I/O L (minimum) Clock Notes
n/a n/a n/a n/a n/a n/a n/a n/a async[1.1] async[1.0] n/a 1.7 1.1 1.1 1.5[1.0] 1.5[1.1] n/a [1.0][1.8] [1.3][2.2] [1.1][2.2] [1.0][1.9] [1.4][2.2] [1.3][2.1] n/a [1.0] [2.1] [1.0][1.9] n/a
n/a n/a n/a n/a n/a n/a n/a n/a async[0.9] async[1.3] n/a 1.6 0.9 0.2 1.7[1.1] 1.6[1.0] n/a [3.5][0.7] [3.0][0.3] [3.0][0.3] [3.3][0.7] [2.2][0.3] [2.6][0.8] n/a [2.6] [0.0] [3.2][0.6] n/a
12 12 12 12 12 12 12 12 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
8 8 8 8 8 8 8 8 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
PHYTX PHYTX
1 1
1 1 1, async PHYRX PHYRX PHYRX 1 1 1 1, async
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DS2011
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NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 15. I/O Specifications--133 and 200MHz (Sheet 2 of 3)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal HDLCEXTxClk HDLCEXTxDataA:B HDLCEXTxFS [HDLCEXTxEnA:B] HDLCMP Interface HDLCMPTxClk0:3 [HDLCMPTxClk4:7] HDLCMPTxData0:3 [HDLCMPTxData4] [HDLCMPTxData5] [HDLCMPTxData6] [HDLCMPTxData7] [HDLCMPTxEn0] [HDLCMPTxEn1] [HDLCMPTxEn2] [HDLCMPTxEn3] [HDLCMPTxEn4] [HDLCMPTxEn5] [HDLCMPTxEn6] [HDLCMPTxEn7] HDLCMPRxClk0:3 [HDLCMPRxClk4:7] HDLCMPRxData0:3 [HDLCMPRxData4] [HDLCMPRxData5] [HDLCMPRxData6] [HDLCMPRxData7] Trace Interface [TrcClk] [TS1E] [TS2E] [TS1O] [TS2O] [TS3:4] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a [12.2] [7.2] [7.2] [7.2] [7.2] [7.2] [2.5] [2.0] [2.0] [2.0] [2.0] [2.0] 12 12 12 12 12 12 8 8 8 8 8 8 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 22.8 [24.9] [24.7] [24.6] [24.8] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 0.5 [0.1] [0.1] [0.1] [0.1] n/a n/a 9.3 [9.9] [9.8] [9.8] [9.8] [10.0] [9.9] [9.4] [9.5] [9.9] [9.8] [9.8] [9.9] n/a n/a n/a n/a n/a n/a n/a n/a n/a 3.0 [3.3] [2.8] [3.0] [3.0] [2.9] [2.9] [2.9] [2.9] [3.3] [2.8] [3.0] [3.0] n/a n/a n/a n/a n/a n/a n/a n/a n/a 12 12 12 12 12 12 12 12 12 12 12 12 12 n/a n/a n/a n/a n/a n/a n/a n/a n/a 8 8 8 8 8 8 8 8 8 8 8 8 8 n/a n/a n/a n/a n/a n/a n/a Setup Time (TIS min) n/a n/a 24.4 n/a Hold Time (TIH min) n/a n/a 0.7 n/a Output (ns) Valid Delay (TOV max) n/a 10.5 n/a 9.9 Hold Time (TOH min) n/a 3.3 n/a 3.0 Output Current (mA) I/O H (maximum) n/a 12 n/a 12 I/O L (minimum) n/a 8 n/a 8 Clock Notes
AMCC Proprietary
DS2011
63
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 15. I/O Specifications--133 and 200MHz (Sheet 3 of 3)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal SDRAM Interface BA1:0 BankSel3:0 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:00 MemData00:31 RAS WE [DMAReq0:3] [DMAAck0:3] [EOT0:3/TC0:3] PerAddr04:31 PerBLast PerCS0 [PerCS1:7] PerData00:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 PerClk PerErr BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq IIC EEPROM Controller IECSCL IECSDA aysnc aysnc aysnc aysnc aysnc aysnc aysnc aysnc 17 17 11 11 n/a n/a n/a n/a n/a n/a 2.7 n/a 2.8 n/a n/a [4.7] n/a [4.5] 3.0 4.2 n/a n/a 5.7 n/a 3.4 4.5 7.6 3.0 n/a 2.9 n/a n/a 4.5 n/a n/a 2.9 4.0 n/a n/a n/a n/a n/a n/a 1.0 n/a 1.0 n/a n/a [0.0] n/a [0.0] 1.0 0.0 n/a n/a 1.0 n/a 0.0 0.0 0.0 0.0 n/a 0.0 n/a n/a 0.0 n/a n/a 0.0 0.0 7.1 5.2 6.8 4.5 5.3 5.3 5.2 7.0 5.2 6.7 5.5 n/a [8.5] [8.6] 8.5 7.1 8.7 [8.7] 9.5 7.5 8.9 7.5 n/a 7.7 -0.6 n/a 6.8 6.9 n/a 8.0 7.3 n/a n/a 1.1 0.5 1.0 0.5 0.5 0.5 0.5 1.0 0.5 0.9 1.5 n/a [1.0] [1.0] 1.0 1.2 1.0 [1.0] 1.3 1.3 1.1 1.2 n/a 1.3 -0.7 n/a 1.2 1.2 n/a 0.0 1.4 n/a n/a 19 19 19 40 19 19 19 19 19 19 19 n/a 12 12 17 12 12 12 17 12 17 12 n/a 12 17 n/a 12 12 n/a 19 12 n/a n/a 12 12 12 25 12 12 12 12 12 12 12 n/a 8 8 11 8 8 8 11 8 11 8 n/a 8 11 n/a 8 8 n/a 12 8 n/a n/a MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk 5 2, 3 3 2, 3 3 3 3 3 2, 3 3 2, 3 2, 3 Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (maximum) I/O L (minimum) Clock Notes
External Slave Peripheral Bus Interface
External Master Peripheral Bus Interface
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DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
I/O SPECIFICATIONS(A)--266 MHZ
Table 16. I/O Specifications--266MHz (Sheet 1 of 3)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal Setup Time (TIS min) n/a 100 n/a Hold Time (TIH min) n/a 0.0 n/a Output (ns) Valid Delay (TOV max) n/a Hold Time (TOH min) n/a Output Current (mA) I/O H (maximum) 12 12 12 I/O L (minimum) 8 8 8 EMC0MDClk PHYTX Clock Notes
Ethernet Interface
EMC0MDClk EMC0MDIO EMC0TxD0:3 [EMC0Tx0:1D0:1] [EMC0Tx0:3D] EMC0TxEn [EMC0Tx0En] [EMC0Sync] EMC0TxErr[EMC0Tx1En] [EMC1TxD0][EMC1Tx2D0] [EMC1TxD1][EMC1Tx2D1] [EMC1TxD2][EMC1Tx3D0] [EMC1TxD3][EMC1Tx3D1] [EMC1TxEn][EMC1Tx2En] [EMC1TxErr][EMC1Tx3En] PHY0Col[PHY0Rx1Er]l PHY0CrS[PHY0CrS0DV] PHY0RxClk PHY0RxD0:3 [PHY0Rx0:1D0:1] [PHY0Rx0:3D] PHY0RxDV[PHY0CRS1DV] PHY0RxErr[PHY0Rx0Er] PHY0TxClk[PHY0RefClk] [PHY1RxD0][PHY1Rx2D0] [PHY1RxD1][PHY1Rx2D1] [PHY1RxD2][PHY1Rx3D0] [PHY1RxD3][PHY1Rx3D1] [PHY1Col][PHY1Rx3Er] [PHY1CrS][PHY1CrS2DV] [PHY1RxClk] [PHY1RxDV] [PHY1CrS3DV] [PHY1RxErr][PHY1Rx2Er] [PHY1TxClk] 1, async 1 1 1 OPB clock 1 OPB clock period +10ns period 9.0 [5.3] [4.6] 11.4 [5.2] [4.6] 10.8[5.4] [11.3[6.5] [10.9][6.1] [10.9][6.1] [11.4][6.5] [12.7][6.2] [12.7][6.0] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 4.1 [2.3] [1.5] 4.3 [2.3] [1.5] 4.0[2.3] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5]] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
n/a n/a n/a n/a n/a n/a n/a n/a async[1.0] async[1.0] n/a 1.7 [1.1] [1.1] 1.5[1.1] 1.5[1.1] n/a [1.0][1.5] [1.2][1.8] [1.1][1.8] [0.9][1.5] [1.4[2.0] [1.3][1.9] n/a 1.1 [1.8] [1.0][1.6] n/a n/a 25.6 24.2
n/a n/a n/a n/a n/a n/a n/a n/a async[0.7] async[0.9] n/a 1.2 [0.7] [0.1] 1.2[0.8] 1.2[0.8] n/a [2.6][0.5] [2.2][0.3] [2.2][0.3] [2.5][0.5] [1.5][0.2] [1.8][0.5] n/a 2.0 [0.1] [2.4][0.4] n/a n/a 1.1 0.5
12 12 12 12 12 12 12 12 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
8 8 8 8 8 8 8 8 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
PHYTX PHYTX
1 1
1 1 1, async PHYRX PHYRX PHYRX 1 1 1 1, async
HDLCEX Interface
HDLCEXRxClk HDLCEXRxDataA:B HDLCEXRxFS AMCC Proprietary
DS2011
65
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 16. I/O Specifications--266MHz (Sheet 2 of 3)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal HDLCEXTxClk HDLCEXTxDataA:B HDLCEXTxFS [HDLCEXTxEnA:B] Setup Time (TIS min) n/a n/a 24.3 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 21.1 [24.8] [24.7] [24.7] [24.8] n/a n/a n/a n/a n/a n/a Hold Time (TIH min) n/a n/a 0.5 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 0.4 [0.1] [0.1] [0.1] [0.1] n/a n/a n/a n/a n/a n/a Output (ns) Valid Delay (TOV max) n/a 7.2 n/a [7.4] n/a n/a 7.3 [7.5] [7.4] [7.3] [7.4] [7.4] [7.5] [7.8] [7.4] [7.4] n/a n/a n/a n/a n/a n/a n/a [9.5] [5.9] [5.9] [5.9] [5.9] [5.9] Hold Time (TOH min) n/a 3.1 n/a [3.2] n/a n/a 3.1 [3.2] [2.9] [3.0] [3.0] [2.8] [3.2] [3.1] [3.0] [3.0] n/a n/a n/a n/a n/a n/a n/a [2.5] [2.0] [2.0] [2.0] [2.0] [2.0] Output Current (mA) I/O H (maximum) n/a 12 n/a 12 n/a n/a 12 12 12 12 12 12 12 12 12 12 n/a n/a n/a n/a n/a n/a n/a 12 12 12 12 12 12 I/O L (minimum) n/a 8 n/a 8 n/a n/a 8 8 8 8 8 8 8 8 8 8 n/a n/a n/a n/a n/a n/a n/a 8 8 8 8 8 8 Clock Notes
HDLCMP Interface
HDLCMPTxClk0:3 [HDLCMPTxClk4:7] HDLCMPTxData0:3 [HDLCMPTxData4] [HDLCMPTxData5] [HDLCMPTxData6] [HDLCMPTxData7] [HDLCMPTxEn0:3] [HDLCMPTxEn4] [HDLCMPTxEn5] [HDLCMPTxEn6] [HDLCMPTxEn7] HDLCMPRxClk0:3 [HDLCMPRxClk4:7] HDLCMPRxData0:3 [HDLCMPRxData4] [HDLCMPRxData5] [HDLCMPRxData6] [HDLCMPRxData7]
Trace Interface
[TrcClk] [TS1E] [TS2E] [TS1O] [TS2O] [TS3:6]
66
DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Table 16. I/O Specifications--266MHz (Sheet 3 of 3)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal Setup Time (TIS min) n/a n/a n/a n/a n/a n/a 1.6 n/a 1.6 n/a n/a [3.8] n/a [3.5] 2.4 3.0 n/a n/a 4.4 n/a 2.7 3.5 5.8 2.4 n/a 2.3 n/a n/a 3.5 n/a n/a 2.3 3.2 async async Hold Time (TIH min) n/a n/a n/a n/a n/a n/a 1.0 n/a 1.0 n/a n/a [0.0] n/a [0.0] 0.0 0.0 n/a n/a 1.0 n/a 0.0 0.0 0.0 0.0 n/a 0.0 n/a n/a 0.0 n/a n/a 0.0 0.0 async async Output (ns) Valid Delay (TOV max) 6.0 4.7 5.7 4.2 4.7 4.7 4.8 6.0 4.8 5.7 6.2 n/a [6.1] [6.4] 6.6 5.3 5.3 [7.1] 7.2 7.5 6.9 5.6 n/a 5.7 0.0 n/a 5.0 5.1 n/a 8.0 5.4 n/a n/a async async Hold Time (TOH min) 1.8 1.2 1.7 1.2 1.2 1.2 1.2 1.7 1.2 1.6 2.2 n/a [1.0] [1.0] 1.0 1.2 1.2 [1.0] 1.2 1.3 1.1 1.2 n/a 1.3 0.7 n/a 1.2 1.2 n/a 0.0 1.4 n/a n/a async async Output Current (mA) I/O H (maximum) 19 19 19 40 19 19 19 19 19 19 19 n/a 12 12 17 12 12 12 17 12 17 12 n/a 12 17 n/a 12 12 n/a 19 12 n/a n/a 17 17 I/O L (minimum) 12 12 12 25 12 12 12 12 12 12 12 n/a 8 8 11 8 8 8 11 8 11 8 n/a 8 11 n/a 8 8 n/a 12 8 n/a n/a 11 11 Clock Notes
SDRAM Interface
BA1:0 BankSel3:0 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:00 MemData00:31 RAS WE [DMAReq0:3] [DMAAck0:3] [EOT0:3/TC0:3] PerAddr04:31 PerBLast PerCS0 [PerCS1:7] PerData00:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 PerClk PerErr BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk 5 2, 3 3 2, 3 3 3 3 3 2, 3 3 2, 3 2, 3
External Slave Peripheral Bus Interface
External Master Peripheral Bus Interface
IIC EEPROM Controller
IECSCL IECSDA
AMCC Proprietary
DS2011
67
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
INITIALIZATION
The following describes the method by which initial chip settings are established when a system reset occurs. Strapping While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial conditions prior to NPe405H start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k to +3.3V or 10k to +5 V, the recommended pulldown is 1k to GND.These pins are used for strap functions only during reset. They are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options.
STRAPPING PIN ASSIGNMENTS
Table 17. Strapping Pin Assignments
Function SEPROMPresent - Serial EEPROM connection to the IIC interface Not connected Connected Option Ball Strapping AJ33 (UART1_Tx) 0 1 H01 (HoldAck) H02 (ExtAck) x 0 1 0 1
When SEPROMPresent = 1, these pins set the highorder two bits of the EEPROM base address. When SEPROMPresent = 0, these pins indicated the width of the boot ROM.
High order EEPROM base address bits 8 bits 16 bits 32 bits reserved
x 0 0 1 1
EEPROM During reset, configuration values other than those obtained from the strapping pins can be read from a serial EEPROM connected to the IIC port. The association of bits in the EEPROM with the configuration values and their default values are covered in detail in the PowerNP NPe405H Network Processor User's Manual. Caution: If SEPROMPresent is strapped to 1, and the EEPROM is not connected or is defective, the NPe405H will not boot up.
68
DS2011
AMCC Proprietary
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
DOCUMENT REVISION HISTORY
Revision 1.01 1.00 Date 04/18/07 07/29/04 Description Updated SDRAM and MDIO timing in Tables 15 and 16. Initial Release
AMCC Proprietary
DS2011
69
NPe405H - PowerNP NPe405H Embedded Processor
Revision 1.01 - April 18, 2007
Data Sheet
Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 -- (800) 755-2622 -- Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC's Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright (c) 2007 Applied Micro Circuits Corporation. 70 DS2011 AMCC Proprietary

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